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MD16R1624AF0-CN9

更新时间: 2023-01-02 17:43:00
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三星 - SAMSUNG 动态存储器
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16页 201K
描述
Rambus DRAM Module, 32MX32, CMOS, RIMM-232

MD16R1624AF0-CN9 数据手册

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Preliminary  
MD16R1624(8/G)AF0  
MD18R1624(8/G)AF0  
32 Bit RIMM® Module  
Overview  
Key Timing Parameters  
®
T h e 3 2 b i t R I M M module is a general purpose high-perfor-  
The following table lists the frequency and latency bins  
a v a i l a b l e f o r 3 2 b i t R I M M m o d u l e s .  
mance line of memory modules suitable for use in a broad  
range of applications including computer memory, personal  
computers, workstations, and other applications where high  
bandwidth and low latency are required.  
Table 1: 32 bit RIMM Module Frequency and Latency  
T h e 3 2 b i t R I M M m o d u l e c o n s i s t s o f 2 5 6 M b / 2 8 8 M b  
R D R A M devices. These are extremely high-speed CMOS  
S p e e d  
®
t
D R A M s o r g a n i z e d a s 1 6 M w o r d s b y 1 6 o r 1 8 b i t s . T h e u s e  
o f R a m b u s S i g n a l i n g L e v e l ( R S L ) t e c h n o l o g y p e r m i t s t h e  
use of conventional system and board design technologies.  
R I M M 3 2 0 0 m o d u l e s s u p p o r t 8 0 0 M H z t r a n s f e r r a t e p e r p i n ,  
resulting in total module bandwidth of 3200MB/s or  
3 . 2 G B / s . R I M M 4 2 0 0 m o d u l e s s u p p o r t 1 0 6 6 M H z t r a n s f e r  
rate per pin, resulting in total module bandwidth of  
4 2 0 0 M B / s o r 4 . 2 G B / s .  
RAC  
O r g a n i -  
( R o w  
A c c e s s  
T i m e )  
n s  
P a r t N u m b e r  
I / O F r e q .  
( M H z )  
z a t i o n  
32  
35  
32  
35  
32  
35  
M D 1 6 / 1 8 R 1 6 2 4 A F 0 - C N 9  
M D 1 6 / 1 8 R 1 6 2 4 A F 0 - C M 9  
M D 1 6 / 1 8 R 1 6 2 8 A F 0 - C N 9  
M D 1 6 / 1 8 R 1 6 2 8 A F 0 - C M 9  
M D 1 6 / 1 8 R 1 6 2 G A F 0 - C N 9  
M D 1 6 / 1 8 R 1 6 2 G A F 0 - C M 9  
3 2 M  
x
1 0 6 6 M H z  
1 0 6 6 M H z  
1 0 6 6 M H z  
3 2 / 3 6  
T h e 3 2 b i t R I M M m o d u l e p r o v i d e s t w o i n d e p e n d e n t 1 6 o r 1 8  
bit memory channels to facilitate compact system design.  
The "Thru" Channel enters and exits the module to support a  
connection to or from a controller, memory slot, or termina-  
t i o n . T h e " T e r m " C h a n n e l i s t e r m i n a t e d o n t h e m o d u l e a n d  
supports a connection from a controller or another memory  
slot.  
6 4 M  
x
R I M M 4 2 0 0  
3 2 / 3 6  
1 2 8 M  
3 2 / 3 6  
x
3 2 M  
x
M D 1 6 / 1 8 R 1 6 2 4 A F 0 - C M 8  
M D 1 6 / 1 8 R 1 6 2 8 A F 0 - C M 8  
M D 1 6 / 1 8 R 1 6 2 G A F 0 - C M 8  
3 2 / 3 6  
T h e R D R A M a r c h i t e c t u r e e n a b l e s t h e h i g h e s t s u s t a i n e d  
bandwidth for multiple, simultaneous, randomly addressed  
memory transactions. The separate control and data buses  
w i t h i n d e p e n d e n t r o w a n d c o l u m n c o n t r o l y i e l d o v e r 9 5 %  
bus efficiency. The RDRAM device multi-bank architecture  
supports up to four simultaneous transactions per device.  
6 4 M  
x
R I M M 3 2 0 0  
8 0 0 M H z  
40  
3 2 / 3 6  
1 2 8 M  
3 2 / 3 6  
x
Features  
¨
2 I n d e p e n d e n t R D R A M c h a n n e l s , 1 p a s s t h r o u g h a n d 1  
t e r m i n a t e d o n 3 2 b i t R I M M m o d u l e  
Form Factor  
¨
¨
¨
H i g h s p e e d 8 0 0 a n d 1 0 6 6 M H z R D R A M d e v i c e s  
2 3 2 e d g e c o n n e c t o r p a d s w i t h 1 m m p a d s p a c i n g  
M o d u l e P C B s i z e : 1 3 3 . 3 5 m m x 3 4 . 9 3 m m x 1 . 2 7 m m  
(5. 25” x 1. 375” x 0. 05” )  
T h e 3 2 b i t R I M M m o d u l e s a r e o f f e r e d i n 2 3 2 - p a d 1 m m e d g e  
c o n n e c t o r p a d p i t c h s u i t a b l e f o r 2 3 2 c o n t a c t R I M M c o n n e c -  
t ors.  
¨
¨
¨
¨
¨
Gold plated edge connector pad contacts  
Serial Presence Detect (SPD) support  
Operates from a 2. 5 volt supply (±5 % )  
L o w p o w e r a n d p o w e r d o w n s e l f r e f r e s h m o d e s  
S e p a r a t e R o w a n d C o l u m n b u s e s f o r h i g h e r e f f i c i e n c y  
Figure 1 : 32 bit RIMM module with heat spreader  
Page1  
Version 1.0 July 2002  

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