16-bit Microcontroller
MC9S12NE64
Features
Benefits
Target Applications
High-Performance 16-bit HCS12 CPU Core
> Industrial Controls
> Network Appliances
> Remote Equipment
> Ethernet-Enabled Games
> Ethernet Bridge
> Automotive Meter
Reading
> 25 MHz operation at 3.3 V for 40 nsec
minimum instruction cycle time
> Object code compatible with the 68HC11
and 68HC12
> Vending Machines
> Home/Office Automation
> C-optimized architecture produces extremely
compact code
On-Chip Debug Interface
> Single-wire background debug mode
> Real-time emulation of MCU functions at full
operating voltage and frequency range
without the limitations of traditional emulators
> On-chip trace buffer with nine flexible trigger
modes and multiple hardware breakpoints
The HCS12 family of microcontrollers is the next
generation of the highly successful 68HC12 architecture.
Using Freescale Semiconductor’s 0.25µ Flash, the
MC9S12NE64 provides an upward migration path from the
68HC08, 68HC11 and 68HC12 architectures for
applications that need larger memory, more peripherals and
higher performance.
> Real-time in-circuit emulation and debug
without expensive and cumbersome
“box” emulators
> Nonintrusive emulation
> Read/write memory and registers while
running at full speed
> Bus state analysis without the expense of a
traditional emulator
The MC9S12NE64 provides a total Ethernet connectivity
solution in one microcontroller unit (MCU) with its integrated
Ethernet Media Access Controller (EMAC), 10/100
Ethernet physical layer (EPHY) and on-chip Flash memory.
Integrated Third-Generation Flash Memory
> In-application reprogrammable
> Flexibility to change code in the field
> Efficient end-of-line programming
> Self-timed, fast programming
Other features include two serial communications interfaces
(SCIs), a four-channel timer, a serial peripheral interface
(SPI), an inter-integrated circuit (I C) and a 10-bit analog
• Fast Flash page erase—20 µs (512 bytes)
> Total program time for 64K code is less than
five seconds
• Can program 16 bits in 20 µs while in
burst mode
2
> Reduces production programming cost
through ultrafast programming
to digital converter (ADC).
> Internal program/erase voltage generation
> No external high voltage or charge
pump required
> Flash granularity—512 byte Flash erase/
2 byte Flash program
> Virtual EEPROM implementation, Flash
array usable for EE emulation
BLOCK DIAGRAM
> Flexible block protection and security
10/100 Mbps Ethernet Media Access Controller
> IEEE® 802.3-compliant MAC
HCS12 CPU with Debug Module
> Industry standard
> Standard Media Independent Interface (MII)
and MII management interface
> Improved interoperability
> Enhancement of CPU bandwidth
with filtering
64K Flash
8K RAM
2 x SCI
> Address recognition and filtering
> Programmable MAC buffers: two receive
and one transmit
> Full duplex and flow control
2
SPI
I C
> Hardware address and Ethernet
protocol filtering
Voltage Regulator
10/100 Mbps Ethernet Physical Transceiver
> IEEE 802.3-compliant
3.3 V to 2.5 V Converter
> Self-diagnostic capabilities
> Auto detection of link capabilities
> Enhanced interoperability
EPHY
EMAC
> Half- and full-duplex operation
> Autonegotiation with next page ability
> Digital adaptive equalization
> Integrated wave-shaping circuitry
> Loop back modes
18-Key Wake-up
IRQ Ports
ADC
10-bit, 8-ch.
Timer
16-bit, 4-ch.