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MC74HC137J PDF预览

MC74HC137J

更新时间: 2024-02-10 11:46:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 解码器解复用器
页数 文件大小 规格书
6页 213K
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MC74HC137J 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
The MC74HC137 is identical in pinout to the LS137. The device inputs are  
compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
1
The HC137 decodes a three–bit Address to one–of–eight active–low  
outputs. The device has a transparent latch for storage of the Address. Two  
Chip Selects, one active–low and one active–high, are provided to facilitate  
the demultiplexing, cascading, and chip–selecting functions.  
The demultiplexing function is accomplished by using the Address inputs  
to select the desired device output, and then by using one of the Chip  
Selects as a data input while holding the other one active.  
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
1
ORDERING INFORMATION  
MC74HCXXXN  
MC74HCXXXD  
Plastic  
SOIC  
The HC137 is the inverting version of the HC237.  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
PIN ASSIGNMENT  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
A0  
A1  
A2  
1
2
16  
15  
V
CC  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
3
4
14  
13  
Chip Complexity: 152 FETs or 38 Equivalent Gates  
LATCH ENABLE  
LOGIC DIAGRAM  
5
6
12  
11  
CS2  
CS1  
1
2
3
15  
14  
13  
12  
11  
10  
9
7
8
10  
9
Y7  
A0  
A1  
A2  
Y0  
Y1  
Y2  
Y3  
Y4  
TRANS–  
PARENT  
LATCH  
ADDRESS  
INPUTS  
GND  
1–OF–8  
ACTIVE–  
LOW  
OUTPUTS  
DECODER  
4
LATCH ENABLE  
Y5  
Y6  
FUNCTION TABLE  
7
Y7  
Inputs  
Outputs  
LE CS1 CS2 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7  
6
5
CHIP–  
SELECT  
INPUTS  
CS1  
CS2  
X
X
X
L
H
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
PIN 16 = V  
PIN 8 = GND  
CC  
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H
H
L
X
X
X
*
* = Depends upon the Address previously applied while LE was  
at a low level.  
10/95  
Motorola, Inc. 1995  
REV 6  

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