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MC74HC138A PDF预览

MC74HC138A

更新时间: 2024-01-28 04:14:23
品牌 Logo 应用领域
安森美 - ONSEMI 解码器解复用器
页数 文件大小 规格书
8页 189K
描述
1-of-8 Decoder/Demultiplexer

MC74HC138A 技术参数

是否Rohs认证:不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.92
Is Samacsys:NJESD-30 代码:R-PDIP-T16
JESD-609代码:e0逻辑集成电路类型:OTHER DECODER/DRIVER
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:2/6 V
认证状态:Not Qualified子类别:Decoder/Drivers
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

MC74HC138A 数据手册

 浏览型号MC74HC138A的Datasheet PDF文件第2页浏览型号MC74HC138A的Datasheet PDF文件第3页浏览型号MC74HC138A的Datasheet PDF文件第4页浏览型号MC74HC138A的Datasheet PDF文件第5页浏览型号MC74HC138A的Datasheet PDF文件第6页浏览型号MC74HC138A的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74HC138A is identical in pinout to the LS138. The device  
inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LSTTL outputs.  
http://onsemi.com  
The HC138A decodes a three–bit Address to one–of–eight  
active–low outputs. This device features three Chip Select inputs, two  
active–low and one active–high to facilitate the demultiplexing,  
cascading, and chip–selecting functions. The demultiplexing function  
is accomplished by using the Address inputs to select the desired  
device output; one of the Chip Selects is used as a data input while the  
other Chip Selects are held in their active states.  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
MARKING  
DIAGRAMS  
16  
PDIP–16  
N SUFFIX  
CASE 648  
MC74HC138AN  
AWLYYWW  
16  
16  
1
1
16  
SO–16  
D SUFFIX  
CASE 751B  
HC138A  
AWLYWW  
1
Low Input Current: 1.0 µA  
1
High Noise Immunity Characteristic of CMOS Devices  
16  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
HC  
138A  
ALYW  
TSSOP–16  
DT SUFFIX  
CASE 948F  
16  
Chip Complexity: 100 FETs or 29 Equivalent Gates  
1
1
LOGIC DIAGRAM  
A
= Assembly Location  
1
2
3
15  
14  
13  
12  
A0  
A1  
A2  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
ADDRESS  
INPUTS  
ACTIVE–LOW  
OUTPUTS  
11  
10  
PIN ASSIGNMENT  
9
7
A0  
A1  
1
2
3
4
5
6
7
8
16  
15  
V
CC  
Y0  
14 Y1  
13 Y2  
12 Y3  
A2  
6
4
CS1  
CS2  
CS3  
CHIP–  
SELECT  
INPUTS  
CS2  
PIN 16 = V  
PIN 8 = GND  
CC  
CS3  
CS1  
5
11  
10  
9
Y4  
FUNCTION TABLE  
Y7  
Y5  
Y6  
Inputs  
Outputs  
GND  
CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7  
X
X
L
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
ORDERING INFORMATION  
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Device  
Package  
PDIP–16  
Shipping  
2000 / Box  
48 / Rail  
MC74HC138AN  
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
MC74HC138AD  
SOIC–16  
SOIC–16  
TSSOP–16  
TSSOP–16  
MC74HC138ADR2  
MC74HC138ADT  
MC74HC138ADTR2  
2500 / Reel  
96 / Rail  
H
H
2500 / Reel  
H = high level (steady state); L = low level (steady state); X = don’t care  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 7  
MC74HC138A/D  

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