Datasheet > MC7447AVS1000LB

MC7447AVS1000LB

更新时间： 2024-02-15 04:28:21

品牌	Logo	应用领域
恩智浦 - NXP		时钟外围集成电路
页数	文件大小	规格书
56页	1285K
描述
RISC Microprocessor Hardware Specifications

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技术参数
数据手册

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MC7447AVS1000LB 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	LGA	包装说明：	25 X 25 MM, 2.20 MM HEIGHT, 1.27 MM PITCH, ROHS COMPLIANT, CERAMIC, LGA-360
针数：	360	Reach Compliance Code：	not_compliant
ECCN代码：	3A991	HTS代码：	8542.31.00.01
风险等级：	5.7	其他特性：	ALSO REQUIRES 1.8V OR 2.5V SUPPLY
地址总线宽度：	36	位大小：	32
边界扫描：	YES	最大时钟频率：	167 MHz
外部数据总线宽度：	64	格式：	FLOATING POINT
集成缓存：	YES	JESD-30 代码：	S-CBGA-X360
长度：	25 mm	低功率模式：	YES
湿度敏感等级：	1	端子数量：	360
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	CGA
封装等效代码：	LGA360,19X19,50	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	260
电源：	1.3,1.8/2.5 V	认证状态：	Not Qualified
座面最大高度：	2.2 mm	速度：	1000 MHz
子类别：	Microprocessors	最大供电电压：	1.35 V
最小供电电压：	1.25 V	标称供电电压：	1.3 V
表面贴装：	YES	技术：	CMOS
端子形式：	UNSPECIFIED	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40
宽度：	25 mm	uPs/uCs/外围集成电路类型：	MICROPROCESSOR, RISC
Base Number Matches：	1

MC7447AVS1000LB 数据手册

Features

— Guarantees sequential programming model (precise exception model)

— Monitors all dispatched instructions and retires them in order

— Tracks unresolved branches and flushes instructions after a mispredicted branch

— Retires as many as three instructions per clock cycle

•

Separate on-chip L1 instruction and data caches (Harvard architecture)

— 32-Kbyte, eight-way set-associative instruction and data caches

— Pseudo least-recently-used (PLRU) replacement algorithm

— 32-byte (eight-word) L1 cache block

— Physically indexed/physical tags

— Cache write-back or write-through operation programmable on a per-page or per-block basis

— Instruction cache can provide four instructions per clock cycle; data cache can provide four

words per clock cycle

— Caches can be disabled in software.

— Caches can be locked in software.

— MESI data cache coherency maintained in hardware

— Separate copy of data cache tags for efficient snooping

— Parity support on cache and tags

— No snooping of instruction cache except for icbi instruction

— Data cache supports AltiVec LRU and transient instructions

— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word

forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical

double-word forwarding.

•

Level 2 (L2) cache interface

— On-chip, 512-Kbyte, eight-way set-associative unified instruction and data cache

— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches

— A total 9-cycle load latency for an L1 data cache miss that hits in L2

— Cache write-back or write-through operation programmable on a per-page or per-block basis

— 64-byte, two-sectored line size

— Parity support on cache

Separate memory management units (MMUs) for instructions and data

— 52-bit virtual address, 32- or 36-bit physical address

— Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments

— Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and

memory coherency enforced/memory coherency not enforced on a page or block basis

— Separate IBATs and DBATs (eight each) also defined as SPRs

— Separate instruction and data translation lookaside buffers (TLBs)

– Both TLBs are 128-entry, two-way set-associative, and use an LRU replacement algorithm.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

1 2 3 456 7 8...56

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与MC7447AVS1000LB相关器件

型号	品牌	描述	获取价格	数据表
MC7447AVS1000NB	NXP	RISC Microprocessor Hardware Specifications	获取价格
MC7447AVS1167NB	NXP	RISC Microprocessor Hardware Specifications	获取价格
MC7447AVS1267LB	NXP	RISC Microprocessor Hardware Specifications	获取价格
MC7447AVS1333LB	NXP	32-BIT, 1333MHz, RISC PROCESSOR, CBGA360, 25 X 25 MM, 2.20 MM HEIGHT, 1.27 MM PITCH, ROHS	获取价格
MC7447AVS1420LB	NXP	RISC Microprocessor Hardware Specifications	获取价格
MC7447AVS600NB	NXP	RISC Microprocessor Hardware Specifications	获取价格

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