Datasheet > MC7447AHX1333LB

MC7447AHX1333LB

更新时间： 2024-01-07 11:02:28

品牌	Logo	应用领域
恩智浦 - NXP		时钟外围集成电路
页数	文件大小	规格书
56页	1285K
描述
RISC Microprocessor Hardware Specifications

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MC7447AHX1333LB 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Transferred	零件包装代码：	BGA
包装说明：	25 X 25 MM, 3.24 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360	针数：	360
Reach Compliance Code：	not_compliant	ECCN代码：	3A991.A.1
HTS代码：	8542.31.00.01	风险等级：	5.37
其他特性：	ALSO REQUIRES 1.8V OR 2.5V SUPPLY	地址总线宽度：	36
位大小：	32	边界扫描：	YES
最大时钟频率：	167 MHz	外部数据总线宽度：	64
格式：	FLOATING POINT	集成缓存：	YES
JESD-30 代码：	S-CBGA-B360	JESD-609代码：	e0
长度：	25 mm	低功率模式：	YES
湿度敏感等级：	1	端子数量：	360
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	BGA
封装等效代码：	BGA360,19X19,50	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	260
电源：	1.3,1.8/2.5 V	认证状态：	Not Qualified
座面最大高度：	3.24 mm	速度：	1333 MHz
子类别：	Microprocessors	最大供电电压：	1.35 V
最小供电电压：	1.25 V	标称供电电压：	1.3 V
表面贴装：	YES	技术：	CMOS
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	40	宽度：	25 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR, RISC	Base Number Matches：	1

MC7447AHX1333LB 数据手册

Features

— Four vector units and 32-entry vector register file (VRs)

– Vector permute unit (VPU)

– Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as

vector add instructions (for example, vaddsbs, vaddshs, and vaddsws).

– Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as

vector multiply add instructions (for example, vmhaddshs, vmhraddshs, and

vmladduhm).

– Vector floating-point unit (VFPU)

— Three-stage load/store unit (LSU)

– Supports integer, floating-point, and vector instruction load/store traffic

– Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream

operations

– 3-cycle GPR and AltiVec load latency (byte, half word, word, vector) with 1-cycle

throughput

– 4-cycle FPR load latency (single, double) with 1-cycle throughput

– No additional delay for misaligned access within double-word boundary

– Dedicated adder calculates effective addresses (EAs)

– Supports store gathering

– Performs alignment, normalization, and precision conversion for floating-point data

– Executes cache control and TLB instructions

– Performs alignment, zero padding, and sign extension for integer data

– Supports hits under misses (multiple outstanding misses)

– Supports both big- and little-endian modes, including misaligned little-endian accesses

•

Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions,

respectively, in a cycle. Instruction dispatch requires the following:

— Instructions can only be dispatched from the three lowest IQ entries—IQ0, IQ1, and IQ2.

— A maximum of three instructions can be dispatched to the issue queues per clock cycle.

— Space must be available in the CQ for an instruction to dispatch. (This includes instructions that

are assigned a space in the CQ but not in an issue queue.)

Rename buffers

— 16 GPR rename buffers

— 16 FPR rename buffers

— 16 VR rename buffers

Dispatch unit

•

— Decode/dispatch stage fully decodes each instruction

Completion unit

— The completion unit retires an instruction from the 16-entry completion queue (CQ) when all

instructions ahead of it have been completed, the instruction has finished execution, and no

exceptions are pending.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

1 2 345 6 7...56

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