Datasheet > MC68SZ328P/D

MC68SZ328P/D

更新时间： 2024-02-09 19:07:04

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		便携式
页数	文件大小	规格书
96页	1501K
描述
i.MX Integrated Portable System Processor

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技术参数
数据手册

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MC68SZ328P/D 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.82

MC68SZ328P/D 数据手册

Signals and Connections

Table 3. Signal Names and Descriptions (Continued)

Function/Notes

Signal Name

DQM [3:0]

SDRAM data enable

CSD0

SDRAM/SyncFlash Chip Select signal which is multiplexed with the CS2 signal. These two signals

are selectable by programming the system control register.

CSD1

SDRAM/SyncFlash Chip Select signal which is multiplex with CS3 signal. These two signals are

selectable by programming the system control register. By default, CSD1 is selected, so it can be

used as SyncFlash boot chip select by properly configuring BOOT [3:0] input pins.

RAS

SDRAM/SyncFlash Row Address Select signal

SDRAM/SyncFlash Column Address Select signal

SDRAM/SyncFlash Write Enable signal

SDRAM/SyncFlash Clock Enable 0

SDRAM/SyncFlash Clock Enable 1

SDRAM/SyncFlash Clock

CAS

SDWE

SDCKE0

SDCKE1

SDCLK

RESET_SF

SyncFlash Reset

Clocks and Resets

EXTAL16M

Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when internal oscillator circuit is shut

down.

XTAL16M

EXTAL32K

XTAL32K

CLKO

Crystal output

32 kHz crystal input

32 kHz crystal output

Clock Out signal selected from internal clock signals. Please refer to clock controller for internal

clock selection.

RESET_IN

RESET_OUT

POR

Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all

modules (except the reset module and the clock control module) are reset.

Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from

the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.

Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally

generated by an external RC circuit designed to detect a power-up event.

JTAG

TRST

TDO

TDI

Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.

Serial Output for test instructions and data. Changes on the falling edge of TCK.

Serial Input for test instructions and data. Sampled on the rising edge of TCK.

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor

1...4 5 678 9 10...96

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