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MC56F83663VLH

更新时间： 2024-09-25 19:50:03
品牌 Logo 应用领域
恩智浦 - NXP 外围集成电路
页数 文件大小 规格书
60页 1069K
描述
Digital Signal Processor

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中文翻译

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MC56F83663VLH 技术参数

生命周期：ActiveReach Compliance Code：unknown
风险等级：5.78uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

MC56F83663VLH 数据手册

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Document Number MC56F836XXDS  
Rev. 1.6, 09/2019  
NXP Semiconductors  
Data Sheet: Technical Data  
MC56F836XXDS  
MC56F836xx  
Supports MC56F836xx  
Features  
• Communication interfaces  
– Up to three high-speed queued SCI (QSCI) modules  
with LIN slave functionality  
– Up to two queued SPI (QSPI) modules  
– Two I2C/SMBus ports  
– One FlexCAN module, with Flexible Data-rate  
(CAN-FD) supported  
– One USB2.0 controller with integrated PHY  
• This family of digital signal controllers (DSCs) is  
based on the 32-bit 56800EX core. On a single chip,  
each device combines the processing power of a DSP  
and the functionality of an MCU, with a flexible set of  
peripherals to support many target applications:  
– Industrial control  
– Home appliances  
– General-purpose inverters  
• Timers  
– Smart sensors, fire and security systems  
– Switched-mode power supply and power  
management  
– Two 16-bit quad timer (2 x 4 16-bit timer)  
– Two Periodic Interval Timers (PITs)  
• Security and integrity  
– Power distribution systems  
– Cyclic Redundancy Check (CRC) generator  
– Windowed Computer operating properly (COP)  
watchdog  
– Motor control (ACIM, BLDC, PMSM, SR, stepper)  
– Uninterruptible power supplies (UPS)  
– Solar inverter  
– External Watchdog Monitor (EWM)  
– Medical monitoring applications  
• Clocks  
• DSC based on 32-bit 56800EX core  
– Up to 100 MIPS at 100 MHz core frequency  
– DSP and MCU functionality in a unified, C-efficient  
architecture  
– On-chip relaxation oscillators: 200 kHz, and 48  
MHz IRC  
– Crystal / resonator oscillator  
• System  
• On-chip memory  
– Integrated power-on reset (POR) and low-voltage  
interrupt (LVI) and brown-out reset module  
– Inter-Module Crossbar and Event Generator  
– JTAG/enhanced on-chip emulation (EOnCE) for  
unobtrusive, real-time debugging  
– Up to 2×128 KB dual partition flash memory with  
ECC protection  
– Up to 64 KB data/program RAM  
– Both on-chip flash memory and RAM can be  
mapped into both program and data memory spaces  
– 32 KB boot ROM supports boot from SCI, I2C and  
CAN  
• Operating characteristics  
– Single supply: 2.7 V to 3.6 V  
– 5 V–tolerant I/O (except for 3.3 V RESETB and  
USB_DP/USB_DM pins)  
– Operation ambient temperature: V temperature  
option: -40°C to 105°C  
• Analog  
– Two high-speed, 8-ch external and 2-ch internal, 12-  
bit ADCs with dynamic x1, x2, and x4  
programmable amplifier  
– Four analog comparators with integrated 8-bit DAC  
references  
• 100-pin LQFP, 80-pin LQFP, and 64-pin LQFP  
packages  
• Two standard FlexPWM modules with up to 2x8 PWM  
outputs  
NXP reserves the right to change the production detail specifications as may be  
required to permit improvements in the design of its products.  
1234567...60

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