Datasheet > MC34704AEP

MC34704AEP

更新时间： 2024-04-09 18:58:46

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
54页	2591K
描述
Power Management IC, Multi channel, 8 DC/DC or 5 DC/DC SW Reg, QFN 56

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MC34704AEP 数据手册

PIN CONNECTIONS

Table 2. 34704 Pin Definitions (continued)

A functional description of each pin can be found in the Functional Pin Description section beginning on page 17.

Pin Number Device Pin Name Pin Function

Formal Name

Definition

REG2 Buck Stage

switching node

The inductor is connected between this pin and the SW2U pin.

A/B

SW2D

VOUT2

SW2U

SW5U

VOUT5

SW5D

PVIN5

Input/Output

Output

REG2 regulated output

voltage pin

Connect this pin to the load and to the output filter as close to

the pin as possible.

REG2 Boost Stage

switching node

The inductor is connected between this pin and the SW2D pin.

Input/Output

Output

REG5 Boost Stage

switching node

The inductor is connected between this pin and the SW5D pin.

REG5 regulated output

voltage pin

Connect this pin to the load and to the output filter as close to

the pin as possible.

REG5 Buck Stage

switching node

The inductor is connected between this pin and the SW5U pin.

Input/Output

Power

REG5 power supply input This is the connection to the drain of the high-side switch FET.

voltage

Input decoupling /filtering is required for proper REG5 operation.

Use a 10uf decoupling capacitor for better performance

REG5 Buck Stage

Connect a 1.0 F capacitor between this pin and SW5D pin to

A/B

BT5D

FB5

Passive

Input

bootstrap capacitor input enhance the gate of the Switch Power MOSFET.

REG5 voltage feedback

input for voltage

regulation/programming

Connect the feedback resistor divider to this pin.

REG5 compensation network connection.

REG5 compensation

network connection

A/B

COMP5

PGND

Passive

Ground

Exposed

Pad

Power Ground

Connection for all of the

regulators except REG7

Power Ground Connection for all of the regulators except

REG7. This pad is provided to enhance thermal performance.

Notes

1. If regulator 1 is not used, leave pin 23 Unconnected, All other components should be used to provide VG to the system

2. If regulators 5, 6, 7 and 8 are not used, connect the corresponding pins as follows: FB, SW and VOUT nodes: tied to GND; BT, COMP

and PVIN pins: Not connected; DRV and VREF nodes (REG7 only): Not connected

3. REG 2,3 and 4 should always be populated.

34704

Analog Integrated Circuit Device Data

Freescale Semiconductor

1...4 5 678 9 10...54

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