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MC3456D PDF预览

MC3456D

更新时间: 2024-02-12 17:15:42
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 模拟波形发生功能信号电路光电二极管
页数 文件大小 规格书
10页 204K
描述
DUAL PULSE; RECTANGULAR, TIMER, PDSO14, PLASTIC, SO-14

MC3456D 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP14,.3Reach Compliance Code:unknown
风险等级:5.92JESD-30 代码:R-PDIP-T14
JESD-609代码:e0端子数量:14
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5/15 V
认证状态:Not Qualified子类别:Analog Waveform Generation Functions
表面贴装:NO技术:BIPOLAR
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

MC3456D 数据手册

 浏览型号MC3456D的Datasheet PDF文件第2页浏览型号MC3456D的Datasheet PDF文件第3页浏览型号MC3456D的Datasheet PDF文件第4页浏览型号MC3456D的Datasheet PDF文件第6页浏览型号MC3456D的Datasheet PDF文件第7页浏览型号MC3456D的Datasheet PDF文件第8页 
MC3456  
Figure 13. 1/2 Representative Circuit Schematic  
Control Voltage  
Threshold  
Comparator  
Trigger  
Comparator  
Flip–Flop  
Output  
V
CC  
4.7 k  
830  
4.7 k  
1.0 k  
6.8 k  
5.0 k  
Threshold  
7.0 k  
4.7 k  
3.9 k  
b
Output  
10 k  
c
c b  
e
5.0 k  
5.0 k  
Trigger  
Reset  
220  
Reset  
4.7 k  
100 k  
Discharge  
Gnd  
Discharge  
100  
GENERAL OPERATION  
The MC3456 is a dual timing circuit which uses as its  
timing elements an external resistor/capacitor network. It can  
be used in both the monostable (one shot) and astable  
modes with frequency and duty cycle, controlled by the  
capacitor and resistor values. While the timing is dependent  
upon the external passive components, the monolithic circuit  
provides the starting circuit, voltage comparison and other  
functions needed for a complete timing circuit. Internal to the  
integrated circuit are two comparators, one for the input  
signal and the other for capacitor voltage; also a flip–flop and  
digital output are included. The comparator reference  
voltages are always a fixed ratio of the supply voltage thus  
providing output timing independent of supply voltage.  
that the output is high is given by the equation t = 1.1 R C.  
A
Various combinations of R and C and their associated times  
are shown in Figure 14. The trigger pulse width must be less  
than the timing period.  
A reset pin is provided to discharge the capacitor thus  
interrupting the timing cycle. As long as the reset pin is low,  
the capacitor discharge transistor is turned “on” and prevents  
the capacitor from charging. While the reset voltage is  
applied the digital output will remain the same. The reset pin  
should be tied to the supply voltage when not in use.  
Figure 14. Time Delay  
100  
Monostable Mode  
In the monostable mode, a capacitor and a single resistor  
are used for the timing network. Both the threshold terminal  
and the discharge transistor terminal are connected together  
in this mode (refer to circuit Figure 15). When the input  
10  
1.0  
voltage to the trigger comparator falls below 1/3 V  
the  
CC  
comparator output triggers the flip–flop so that it’s output sets  
low. This turns the capacitor discharge transistor “off” and  
drives the digital output to the high state. This condition  
allows the capacitor to charge at an exponential rate which is  
set by the RC time constant. When the capacitor voltage  
0.1  
0.01  
reaches 2/3 V  
the threshold comparator resets the  
CC  
0.001  
flip–flop. This action discharges the timing capacitor and  
returns the digital output to the low state. Once the flip–flop  
has been triggered by an input signal, it cannot be retriggered  
until the present timing period has been completed. The time  
10  
µs  
100  
µs  
1.0 ms 10 ms  
100 ms  
1.0  
10  
100  
t , TIME DELAY (s)  
d
5
MOTOROLA ANALOG IC DEVICE DATA  

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