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MC14572UB_11

更新时间： 2024-01-21 15:36:39
品牌 Logo 应用领域
安森美 - ONSEMI 栅
页数 文件大小 规格书
6页 115K
描述
Hex Gate

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MC14572UB_11 数据手册

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MC14572UB  
Hex Gate  
The MC14572UB hex functional gate is constructed with MOS  
P−channel and N−channel enhancement mode devices in a single  
monolithic structure. These complementary MOS logic gates find  
primary use where low power dissipation and/or high noise immunity  
is desired. The chip contains four inverters, one NOR gate and one  
NAND gate.  
http://onsemi.com  
Features  
MARKING  
DIAGRAMS  
• Diode Protection on All Inputs  
• Single Supply Operation  
16  
PDIP−16  
P SUFFIX  
CASE 648  
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
MC14572UBCP  
AWLYYWWG  
• NOR Input Pin Adjacent to V Pin to Simplify Use As An Inverter  
SS  
1
• NAND Input Pin Adjacent to V Pin to Simplify Use As An  
DD  
1
Inverter  
16  
• NOR Output Pin Adjacent to Inverter Input Pin For OR Application  
SOIC−16  
D SUFFIX  
CASE 751B  
14572UBG  
AWLYWW  
• NAND Output Pin Adjacent to Inverter Input Pin For AND  
Application  
1
1
• Capable of Driving Two Low−Power TTL Loads or One  
Low−Power Schottky TTL Load over the Rated Temperature  
Range  
• These Devices are Pb−Free and are RoHS Compliant  
A
= Assembly Location  
= Wafer Lot  
WL  
YY  
WW  
G
= Year  
= Work Week  
= Pb−Free Package  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Parameter  
Symbol  
Value  
Unit  
V
ORDERING INFORMATION  
DC Supply Voltage Range  
V
DD  
−0.5 to +18.0  
†
Input or Output Voltage Range  
(DC or Transient)  
V , V  
in out  
−0.5 to V  
V
Device  
Package  
Shipping  
DD  
+ 0.5  
MC14572UBCPG  
MC14572UBDG  
PDIP−16  
25 Units / Rail  
48 Units / Rail  
Input or Output Current (DC or Transient)  
per Pin  
I , I  
10  
mA  
in out  
(Pb−Free)  
SOIC−16  
(Pb−Free)  
Power Dissipation, per Package (Note 1)  
Ambient Temperature Range  
P
D
500  
mW  
°C  
T
A
−55 to +125  
−65 to +150  
260  
MC14572UBDR2G SOIC−16 2500/Tape & Reel  
(Pb−Free)  
Storage Temperature Range  
T
stg  
°C  
Lead Temperature (8−Second Soldering)  
T
L
°C  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specifications  
Brochure, BRD8011/D.  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. Temperature Derating: Plastic “P and D/DW”  
Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2011  
1
Publication Order Number:  
June, 2011 − Rev. 7  
MC14572UB/D  
 
123456

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