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MC14568BCLS

更新时间： 2024-02-26 08:29:58
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器触发器比较器逻辑集成电路
页数 文件大小 规格书
12页 326K
描述
Counter, CMOS, CDIP16

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中文翻译

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MC14568BCLS 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.92
JESD-30 代码：R-XDIP-T16JESD-609代码：e0
负载/预设输入：YES端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5/15 V
认证状态：Not Qualified筛选级别：MIL-STD-883 Class B (Modified)
子类别：Counters表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
Base Number Matches：1

MC14568BCLS 数据手册

 浏览型号MC14568BCLS的Datasheet PDF文件第2页浏览型号MC14568BCLS的Datasheet PDF文件第3页浏览型号MC14568BCLS的Datasheet PDF文件第4页浏览型号MC14568BCLS的Datasheet PDF文件第5页浏览型号MC14568BCLS的Datasheet PDF文件第6页浏览型号MC14568BCLS的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 620  
The MC14568B consists of a phase comparator, a divide–by–4, 16, 64 or  
100 counter and a programmable divide–by–N 4–bit binary counter (all  
positive–edge triggered) constructed with MOS P–channel and N–channel  
enhancement mode devices (complementary MOS) in a monolithic structure.  
The MC14568B has been designed for use in conjunction with a  
programmable divide–by–N counter for frequency synthesizers and phase–  
locked loop applications requiring low power dissipation and/or high noise  
immunity.  
This device can be used with both counters cascaded and the output of  
the second counter connected to the phase comparator (CTL high), or used  
independently of the programmable divide–by–N counter, for example  
cascaded with a MC14569B, MC14522B or MC14526B (CTL low).  
P SUFFIX  
PLASTIC  
CASE 648  
D SUFFIX  
SOIC  
CASE 751B  
ORDERING INFORMATION  
•
•
Supply Voltage Range = 3.0 to 18 V  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
Capable of Driving Two Low–Power TTL Loads, One Low–Power  
Schottky TTL Load or Two HTL Loads Over the Rated Temperature  
Range.  
T
A
= – 55° to 125°C for all packages.  
•
Chip Complexity: 549 FETs or 137 Equivalent Gates  
MAXIMUM RATINGS* (Voltages referenced to V  
)
SS  
Rating  
DC Supply Voltage  
Symbol  
Value  
Unit  
Vdc  
Vdc  
mAdc  
mW  
C
TRUTH TABLE  
V
DD  
– 0.5 to + 18  
F
G
Pin 11  
Division Ratio  
of Counter D1  
Input Voltage, All Inputs  
V
in  
– 0.5 to V + 0.5  
DD  
Pin 10  
DC Input Current, per Pin  
I
in  
± 10  
0
0
1
1
0
1
0
1
4
16  
64  
Power Dissipation, per Package†  
Operating Temperature Range  
Storage Temperature Range  
P
D
500  
T
A
– 55 to + 125  
– 65 to + 150  
100  
T
stg  
C
The divide by zero state on the pro-  
grammable divide–by–N 4–bit binary  
counter, D2, is illegal.  
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
BLOCK DIAGRAM  
PC 14  
in  
A
B
13 PC  
12 LD  
out  
PHASE  
COMPARATOR  
(REF.)  
TG  
CTL HIGH  
CTL LOW  
TG  
11 G  
10 F  
C1  
9
PC  
in  
PC  
out  
COUNTER D1  
PC  
LD  
PC  
in  
out  
P/C  
D1  
P/C  
D1  
CTL 15  
LD  
TG  
C1  
C1  
“0”  
4–BIT  
PROGRAMMABLE  
COUNTER D2  
“0”  
PE  
3
2
1 Q1/C2  
D2  
D2  
“0”  
Q1/C2  
Q1/C2  
D
D
P0  
P3  
V
V
= PIN 16  
= PIN 8  
DD  
SS  
4
5
P2  
6
P1  
7
D
D
REV 3  
1/94  
Motorola, Inc. 1995  
1234567...12

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