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MC10H351

更新时间： 2024-10-01 22:58:11
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
4页 105K
描述
Quad TTL/NMOS to PECL Translator

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中文翻译

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MC10H351 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
The MC10H351 is a quad translator for interfacing data between a  
saturated logic section and the PECL section of digital systems when only  
a +5.0 Vdc power supply is available. The MC10H351 has TTL/NMOS  
compatible inputs and PECL complementary open–emitter outputs that  
allow use as an inverting/non–inverting translator or as a differential line  
driver. When the common strobe input is at a low logic level, it forces all  
true outputs to the PECL low logic state (≈ +3.2 V) and all inverting  
outputs to the PECL high logic state (≈ +4.1 V).  
P SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
FN SUFFIX  
PLCC  
CASE 775–02  
The MC10H351 can also be used with the MC10H350 to transmit and  
receive TTL/NMOS information differentially via balanced twisted pair  
lines.  
•
•
•
•
Single +5.0 Power Supply  
All V Pins Isolated On Chip  
LOGIC DIAGRAM  
CC  
Differentially Drive Balanced Lines  
= 1.3 nsec Typical  
B IN  
A IN  
D IN  
C IN  
7
1
B OUT  
B OUT  
2
t
pd  
8
5
A OUT  
A OUT  
4
MAXIMUM RATINGS  
12  
16  
17  
19  
18  
D OUT  
D OUT  
C OUT  
C OUT  
Characteristic  
Symbol  
Rating  
Unit  
Vdc  
Vdc  
mA  
Power Supply  
V
CC  
0 to +7.0  
14  
9
Input Voltage (V  
= 5.0 V)  
V
I
0 to V  
50  
CC  
CC  
COMMON  
STROBE  
Output Current— Continuous  
— Surge  
I
out  
100  
V
(+5.0 VDC) = PINS 6, 11, 15, 20  
GND = PIN 10  
CC  
Operating Temperature Range  
T
0 to +75  
°C  
°C  
A
Storage Temperature Range— Plastic  
— Ceramic  
T
stg  
–55 to +150  
–55 to +165  
DIP  
ELECTRICAL CHARACTERISTICS (V  
0°  
= V  
= V  
CC2  
25°  
= 5.0 V ± 5.0%)  
75°  
CC  
CC1  
PIN ASSIGNMENT  
Characteristic  
Symbol Min  
Max  
50  
Min  
—
Max  
Min  
—
Max  
50  
Unit  
mA  
mA  
µA  
B OUT  
B OUT  
N.C.  
ECL V  
CC  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
Power Supply  
Current  
ECL  
TTL  
—
—
45  
15  
C OUT  
C OUT  
D OUT  
D OUT  
20  
—
—
20  
Reverse Current  
Pins 7, 8, 12, 14  
Pin 9  
3
I
—
—
25  
100  
—
—
20  
80  
—
—
25  
100  
R
A OUT  
A OUT  
4
I
INH  
Forward Current  
Pins 7, 8, 12, 14  
Pin 9  
mA  
5
I
—
—
–0.8  
–3.2  
—
—
–0.6  
–2.4  
—
—
–0.8  
–3.2  
F
V
2
I
V
6
CC  
INL  
CC  
Input Breakdown  
Voltage  
V
5.5  
—
5.5  
—
5.5  
—
Vdc  
Vdc  
Vdc  
Vdc  
(BR)in  
C IN  
N.C.  
D IN  
B IN  
7
A IN  
8
Input Clamp Voltage  
(I = –18 mA)  
in  
V
I
—
–1.5  
4.16  
3.37  
—
–1.5  
4.19  
3.37  
—
–1.5  
4.27  
3.37  
COMMON  
STROBE  
9
High Output  
Voltage (1)  
V
3.98  
3.05  
4.02  
3.05  
4.08  
3.05  
OH  
TTL V  
GND  
10  
CC  
Low Output  
Voltage (1)  
V
OL  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–36 of the Motorola MECL Data  
Book (DL122/D).  
High Input Voltage  
Low Input Voltage  
V
2.0  
—
—
2.0  
—
—
2.0  
—
—
Vdc  
Vdc  
IH  
V
0.8  
0.8  
0.8  
IL  
(1) With V  
at 5.0 V. V /V  
OH OL  
change 1:1 with V  
.
CC  
CC  
*Positive Emitter Coupled Logic  
3/93  
Motorola, Inc. 1996  
REV 5  
1234

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