+14dBm to +20dBm LO Buffers/Splitters
with 1dB ꢀariation
Pin Description
PIN
NAME
FUNCTION
1, 4, 8, 9, 13,
17, 18, EP
GND
Ground
2
3
IN
Input. Internally matched 50Ω RF input. AC couple to this pin.
Supply. Supply connection for on-chip voltage and current references. See Applications Information
for information on decoupling.
VCCREF
Voltage Reference Output. Output for on-chip 1.5V bandgap voltage reference. See
Applications Information section for information on decoupling.
5
6
REF
Bias Connection for Input Buffer. Set compressed power point for input amplifier with a resistor to
REF or GND. For +17dBm output power, no external biasing resistors are required. See Applications
Information section for information.
BIASIN
Bias Connection for Output Amplifiers. Set compressed power point for OUT1 and OUT2 with a
resistor to REF or ground. For +17dBm output power, no external biasing resistors are required. See
Applications Information section for information.
7
BIASOUT
10
11, 12
14, 15
16
OUT2
VCC3
Output 2. Internally matched 50Ω RF output. AC couple to this pin.
Supply. Supply connection for OUT2.
VCC2
Supply. Supply connection for OUT1.
OUT1
Output 1. Internally matched 50Ω RF output. AC couple to this pin.
Supply. Supply connection for input amplifier.
19
VCC1
20
OUTPLL
Output PLL. Output for driving optional external PLL.
Input Amplifier
Detailed Description
A single low-noise input amplifier before the passive
splitter provides gain and isolation. The compressed
output power for this stage is controlled by the bias set-
The MAX9987/MAX9988 LO amplifiers/splitters each
consist of a single input amplifier, a two-way passive
power splitter, two separate output amplifiers, as well as
a third buffer amplifier to drive the LO’s PLL. The bias
currents for the amplifiers are adjustable through off-chip
resistors. This allows the output level to be precision set
anywhere from +14dBm to +20dBm. The PLL output is
ting resistors R or R (see Typical Application Circuit).
1
4
These resistors are not required for the nominal +17dBm
output; see Table 1 for bias resistor values to obtain
+14dBm to +20dBm output power.
The input is internally matched to 50Ω, and typical
VSWR is no more than 2:1 over all operating conditions.
Since the input is internally biased, provide a DC block
at the input pin.
preset to +3dBm (about 900mV
into 50Ω).
P-P
Power levels are typically 1dB over the full supply, input
power, frequency, and temperature range. Precision
power control is achieved by internal control circuitry.
Maintaining tight power control keeps the system engi-
neer from over specifying the LO drive in order to guar-
antee a linearity specification in the base-station mixer.
PLL Amplifier and Output
A small amount of power is tapped off from the input
amplifier’s output, and fed to a high-isolation buffer to
drive the PLL output at +3dBm. If the PLL output is not
required, it can be disabled by removing R ; disabling
3
the PLL output saves 12mA supply current.
More than 40dB isolation between the LO outputs and
the input prevents VCO pulling, and the 30dB output-
to-output isolation reduces branch-to-branch coupling.
The MAX9987 is specified from 700MHz to 1100MHz,
and the MAX9988 is specified from 1500MHz to
Passive Two-Way Splitter
The input amplifier drives an integrated power splitter.
All impedance matching between stages is on-chip, so
no external tuning components are required.
✕
2200MHz. Both are offered in compact 5mm 5mm 20-
pin QFN packages with exposed paddle.
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