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MAX97003 PDF预览

MAX97003

更新时间: 2022-11-18 00:17:26
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48页 3976K
描述
High-Efficiency, Low-Noise Audio Subsystem

MAX97003 数据手册

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MAX97003  
High-Efficiency, Low-Noise Audio Subsystem  
ABSOLUTE MAXIMUM RATINGS  
(Voltages with respect to GND.)  
, CPVDD ........................................................-0.3V to +2.2V  
Continuous Current In/Out of PVDD, PGND, SPK_....... Q800mA  
V
Continuous Current In/Out of HPR, HPL, V .............. Q140mA  
DD  
DD  
BIAS.......................................................... -0.3V to (V  
+ 0.3V)  
Continuous Input Current (all other pins)........................ Q20mA  
Duration of SPK_ Short Circuit to GND or PVDD......Continuous  
Duration of Short Circuit Between SPKP and SPKN... Continuous  
DD  
PVDD....................................................................-0.3V to +6.0V  
PGND ...................................................................-0.1V to +0.1V  
CPVSS ................................................................. -2.2V to +0.3V  
Duration of HP_ Short Circuit to GND or V ...........Continuous  
DD  
C1N ................................... (V  
- 0.3V) to (V  
+ 0.3V)  
+ 0.3V)  
+ 0.3V)  
Continuous Power Dissipation (T = +70NC)  
WLP Multilayer Board  
CPVSS  
CPVDD  
CPVDD  
CPVDD  
A
C1P..................................................... -0.3V to (V  
HPL, HPR .......................... (V - 0.3V) to (V  
(derate 21.7mW/NC above +70NC)................................1.74W  
Junction Temperature .....................................................+150NC  
Operating Temperature Range.......................... -40NC to +85NC  
Storage Temperature Range............................ -65NC to +150NC  
Soldering Temperature (reflow) ......................................+260NC  
CPVSS  
INA1, INA2, INB1, INB2 .......................................-0.3V to +6.0V  
SDA, SCL .............................................................-0.3V to +6.0V  
SPKP, SPKN..........................................-0.3V to (V  
+ 0.3V)  
PVDD  
HPSNS..................................................................-0.3V to +0.3V  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-  
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect device reliability.  
ELECTRICAL CHARACTERISTICS  
(V  
= 1.8V, V  
= 4.2V, V  
= V  
= 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal  
DD  
PVDD  
GND  
PGND  
configured single-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential.  
Speaker loads (Z ) connected between SPKP and SPKN. Headphone loads (R ) connected from HPL or HPR to GND. SDA and  
SPK  
HP  
SCL pullup voltage = 1.8V. Z  
= J, R = J. C  
= C  
= C  
= C  
= 1FF. T = T  
to T  
, unless otherwise  
SPK  
HP  
C1P-C1N  
CPVDD  
CPVSS  
BIAS  
A
MIN  
MAX  
noted. Typical values are at T = +25NC.) (Note 1)  
A
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Speaker Amplifier Supply  
Voltage Range  
PVDD  
Guaranteed by PSRR test  
Guaranteed by PSRR test  
2.7  
5.5  
V
Headphone Amplifier Supply  
Voltage Range  
V
1.6  
2
V
DD  
HP mode, T = +25NC, stereo  
SE input on INA routed to HP  
output, HP expander disabled  
A
I
I
I
I
1.21  
1.07  
2.46  
1.34  
1.6  
1.3  
VDD  
PVDD  
VDD  
HP mode, T = +25NC, stereo  
A
2.95  
1.6  
SE input on INA routed to HP  
output, HP expander enabled  
PVDD  
SPK mode, T = +25NC mono  
A
I
I
I
I
0.1  
2.25  
1.35  
2.6  
0.15  
2.6  
VDD  
differential input on INA routed  
to SPK output; SPK expander,  
DRC, and limiter all disabled  
PVDD  
VDD  
Quiescent Current  
I
mA  
DD  
SPK mode, T = +25NC mono  
A
1.65  
2.95  
differential input on INA routed  
to SPK output; SPK expander,  
DRC, and limiter all enabled  
PVDD  
SPK + HP mode, T = +25NC  
stereo SE input on INA routed  
to HP and SPK output; SPK and  
HP expanders, DRC, and limiter  
all disabled  
A
I
1.21  
2.74  
1.6  
3.2  
VDD  
I
PVDD  
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