5秒后页面跳转
MAX7314AEG+ PDF预览

MAX7314AEG+

更新时间: 2024-02-01 18:53:16
品牌 Logo 应用领域
美信 - MAXIM 信息通信管理光电二极管外围集成电路
页数 文件大小 规格书
25页 319K
描述
Parallel I/O Port, 8-Bit, 16 I/O, BICMOS, PDSO24, 0.150 INCH, 0.025 INCH PITCH, MO-137, QSOP-24

MAX7314AEG+ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SSOP
包装说明:SSOP, SSOP24,.24针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:1.71JESD-30 代码:R-PDSO-G24
JESD-609代码:e3长度:8.65 mm
湿度敏感等级:1位数:8
I/O 线路数量:16端口数量:1
端子数量:24最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP24,.24
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:2.5/3.3 V
认证状态:Not Qualified座面最大高度:1.73 mm
子类别:Parallel IO Port最大供电电压:3.6 V
最小供电电压:2 V标称供电电压:3.3 V
表面贴装:YES技术:BICMOS
温度等级:AUTOMOTIVE端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmuPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches:1

MAX7314AEG+ 数据手册

 浏览型号MAX7314AEG+的Datasheet PDF文件第5页浏览型号MAX7314AEG+的Datasheet PDF文件第6页浏览型号MAX7314AEG+的Datasheet PDF文件第7页浏览型号MAX7314AEG+的Datasheet PDF文件第9页浏览型号MAX7314AEG+的Datasheet PDF文件第10页浏览型号MAX7314AEG+的Datasheet PDF文件第11页 
18-Port GPIO with LED Intensity Control,  
Interrupt, and Hot-Insertion Protection  
The MAX7314 SDA line operates as both an input and  
Serial Interface  
an open-drain output. A pullup resistor, typically 4.7kΩ,  
is required on the SDA. The MAX7314 SCL line oper-  
ates only as an input. A pullup resistor, typically 4.7kΩ,  
is required on SCL if there are multiple masters on the  
2-wire interface, or if the master in a single-master sys-  
tem has an open-drain SCL output.  
Serial Addressing  
The MAX7314 operates as a slave that sends and  
receives data through an I2C-compatible 2-wire inter-  
face. The interface uses a serial data line (SDA) and a  
serial clock line (SCL) to achieve bidirectional commu-  
nication between master(s) and slave(s). A master (typ-  
ically a microcontroller) initiates all data transfers to and  
from the MAX7314 and generates the SCL clock that  
synchronizes the data transfer (Figure 2).  
Each transmission consists of a START condition  
(Figure 3) sent by a master, followed by the MAX7314  
7-bit slave address plus R/W bit, a register address  
byte, one or more data bytes, and finally a STOP condi-  
tion (Figure 3).  
Start and Stop Conditions  
Both SCL and SDA remain high when the interface is  
not busy. A master signals the beginning of a transmis-  
sion with a START (S) condition by transitioning SDA  
from high to low while SCL is high. When the master  
has finished communicating with the slave, it issues a  
STOP (P) condition by transitioning SDA from low to  
high while SCL is high. The bus is then free for another  
transmission (Figure 3).  
SDA  
SCL  
S
P
START  
STOP  
CONDITION  
CONDITION  
Figure 3. Start and Stop Conditions  
Bit Transfer  
One data bit is transferred during each clock pulse.  
The data on SDA must remain stable while SCL is high  
(Figure 4).  
SDA  
SCL  
Acknowledge  
The acknowledge bit is a clocked 9th bit that the recipi-  
ent uses to handshake receipt of each byte of data  
(Figure 5). Thus, each byte transferred effectively  
requires 9 bits. The master generates the 9th clock  
pulse, and the recipient pulls down SDA during the  
acknowledge clock pulse so the SDA line is stable low  
during the high period of the clock pulse. When the  
master is transmitting to the MAX7314, the device gen-  
erates the acknowledge bit because the MAX7314 is  
the recipient. When the MAX7314 is transmitting to the  
master, the master generates the acknowledge bit  
because the master is the recipient.  
DATA LINE STABLE; CHANGE OF DATA  
DATA VALID  
ALLOWED  
Figure 4. Bit Transfer  
CLOCK PULSE  
FOR ACKNOWLEDGE  
START  
CONDITION  
SCL  
1
2
8
9
SDA BY  
TRANSMITTER  
Slave Address  
The MAX7314 has a 7-bit long slave address (Figure 6).  
The eighth bit following the 7-bit slave address is the  
R/W bit. The R/W bit is low for a write command, high  
for a read command.  
SDA BY  
RECEIVER  
S
Figure 5. Acknowledge  
SDA  
SCL  
A6  
1
0
0
A2  
0
0
R/W  
ACK  
LSB  
MSB  
Figure 6. Slave Address  
_______________________________________________________________________________________  
8

与MAX7314AEG+相关器件

型号 品牌 描述 获取价格 数据表
MAX7314AEG+T MAXIM Parallel I/O Port, 8-Bit, 16 I/O, BICMOS, PDSO24, 0.150 INCH, 0.025 INCH PITCH, MO-137, QS

获取价格

MAX7314AEG-T MAXIM Parallel I/O Port, 8-Bit, 16 I/O, BICMOS, PDSO24, 0.150 INCH, 0.025 INCH PITCH, MO-137, QS

获取价格

MAX7314ATG MAXIM 18-Port GPIO with LED Intensity Control, Interrupt, and Hot-Insertion Protection

获取价格

MAX7314ATG+ MAXIM Parallel I/O Port, 8-Bit, 16 I/O, BICMOS, 4 X 4 MM, 0.80 MM HEIGHT, MO-220WGGD2, TQFN-24

获取价格

MAX7314ATG+T MAXIM Parallel I/O Port, 8-Bit, 16 I/O, BICMOS, 4 X 4 MM, 0.80 MM HEIGHT, MO-220WGGD2, TQFN-24

获取价格

MAX7314ATG-T MAXIM Parallel I/O Port, 8-Bit, 16 I/O, BICMOS, 4 X 4 MM, 0.80 MM HEIGHT, MO-220WGGD2, TQFN-24

获取价格