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MAX5166 PDF预览

MAX5166

更新时间: 2024-01-09 20:44:22
品牌 Logo 应用领域
美信 - MAXIM 放大器
页数 文件大小 规格书
12页 178K
描述
32-Channel Sample/Hold Amplifier with Four Multiplexed Inputs

MAX5166 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QFP包装说明:TQFP-48
针数:48Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.33.00.01
风险等级:5.91Is Samacsys:N
最长采集时间:4 µs标称采集时间:2.5 µs
放大器类型:SAMPLE AND HOLD CIRCUIT最大模拟输入电压:7 V
最小模拟输入电压:-4 V最大下降率:0.04 V/s
JESD-30 代码:S-PQFP-G48JESD-609代码:e0
长度:7 mm湿度敏感等级:1
标称负供电电压 (Vsup):-5 V功能数量:1
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP48,.35SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):245电源:10,-5,5 V
认证状态:Not Qualified采样并保持/跟踪并保持:SAMPLE
座面最大高度:1.6 mm子类别:Sample and Hold Circuits
标称供电电压 (Vsup):10 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
Base Number Matches:1

MAX5166 数据手册

 浏览型号MAX5166的Datasheet PDF文件第4页浏览型号MAX5166的Datasheet PDF文件第5页浏览型号MAX5166的Datasheet PDF文件第6页浏览型号MAX5166的Datasheet PDF文件第8页浏览型号MAX5166的Datasheet PDF文件第9页浏览型号MAX5166的Datasheet PDF文件第10页 
32-Channel Sample/Hold Amplifier  
with Four Multiplexed Inputs  
Table 1. Output Selection  
ADDRESS  
OUTPUT SELECTED  
A2  
0
A1  
0
A0  
0
MUX0  
OUT0  
OUT1  
OUT2  
OUT3  
OUT4  
OUT5  
OUT6  
OUT7  
MUX1  
OUT8  
MUX2  
OUT16  
OUT17  
OUT18  
OUT19  
OUT20  
OUT21  
OUT22  
OUT23  
MUX3  
OUT24  
OUT25  
OUT26  
OUT27  
OUT28  
OUT29  
OUT30  
OUT31  
0
0
1
OUT9  
0
1
0
OUT10  
OUT11  
OUT12  
OUT13  
OUT14  
OUT15  
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0 = Logic Low, 1 = Logic High  
Note: Output loads increase the analog supply cur-  
rent (I and I ). Excessive loading of the output(s)  
damages the device by consuming more power than  
the device will dissipate (see Absolute Maximum  
Ratings). The resistor-divider formed by the output  
Table 2. Mode Selection  
DD  
SS  
MODE-SELECT  
INPUTS* (M3–M0)  
ACTION  
Sample mode enabled on selected  
analog multiplexer and channel  
(Table 1).  
resistor (ꢀ  
) and load impedance (ꢀ ) scales the  
L
SAMP  
) as follows:  
OUT_  
0
1
sampled voltage (V  
). Determine the output volt-  
age (V  
OUT_  
Hold mode enabled on selected  
analog multiplexer and channel  
(Table 1).  
Voltage Gain = A = ꢀ /(ꢀ + ꢀ  
)
V
L
L
OUT  
V
OUT_  
= V · A  
SAMP V  
The maximum output voltage range depends on the  
analog supply voltages available and the scaling factor  
used:  
0 = Logic Low, 1 = Logic High  
* Only one M_ input asserted low; all others must be logic high  
to meet the timing specification (see Single vs. Simultaneous  
Sampling).  
(V + 0.75V) · A  
V
OUT_  
(V - 2.4V) · A  
DD V  
SS  
V
when ꢀ = , then A = 1, and this equation becomes  
L
V
Hold Step  
When switching between sample mode and hold  
mode, the voltage of the hold capacitor changes due to  
charge injection from stray capacitance. This voltage  
change, called hold step, is minimized by limiting the  
amount of stray capacitance seen by the hold capaci-  
tor. The MAX5166 limits the hold step to 0.25mV (typ).  
An output capacitor to ground can be used to filter out  
this small hold-step error.  
(V + 0.75V)  
V
(V  
- 2.4V).  
SS  
OUT  
DD  
Timing Definitions  
Acquisition time (t ) is the amount of time the  
AQ  
MAX5166 must remain in sample mode for the hold  
capacitor to acquire an accurate sample. The hold-  
mode settling time (t ) is the amount of time necessary  
H
for the output voltage to settle to its final value.  
Aperture delay (t ) is the time interval required to dis-  
AP  
connect the input from the hold capacitor. The inhibit  
Output  
The MAX5166 contains an output buffer for each multi-  
plexer channel (32 total), so the hold capacitor sees a  
high-impedance input, reducing the droop rate. While  
in hold mode, the hold capacitor discharges at a rate of  
1mV/sec (typ). The buffer also provides a low output  
impedance; however, the device contains output resis-  
tors in series with the buffer output (Figure 1) for select-  
ed output filtering. To provide greater design flexibility,  
pulse width (t ) is the amount of time the MAX5166  
PW  
must remain in hold mode while the address is  
changed. The data setup time (t ) is the amount of  
DS  
time an address must be maintained before the  
address becomes valid. The data hold time (t ) is the  
DH  
amount of time an address must be maintained after  
mode select has gone from low to high (Figure 2).  
the MAX5166 is available with an ꢀ of 50 , 500 , or  
O
1k .  
_______________________________________________________________________________________  
7

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