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MAX3881ECB+TD PDF预览

MAX3881ECB+TD

更新时间: 2024-01-23 06:03:12
品牌 Logo 应用领域
美信 - MAXIM 时钟
页数 文件大小 规格书
11页 234K
描述
Clock Recovery Circuit, 1-Func, Bipolar, PQFP64, 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, TQFP-64

MAX3881ECB+TD 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:HTFQFP,
针数:64Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.9
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:10 mm湿度敏感等级:3
功能数量:1端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HTFQFP
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):245认证状态:Not Qualified
座面最大高度:1.2 mm标称供电电压:3.3 V
表面贴装:YES技术:BIPOLAR
电信集成电路类型:ATM/SONET/SDH CLOCK RECOVERY CIRCUIT温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
Base Number Matches:1

MAX3881ECB+TD 数据手册

 浏览型号MAX3881ECB+TD的Datasheet PDF文件第3页浏览型号MAX3881ECB+TD的Datasheet PDF文件第4页浏览型号MAX3881ECB+TD的Datasheet PDF文件第5页浏览型号MAX3881ECB+TD的Datasheet PDF文件第7页浏览型号MAX3881ECB+TD的Datasheet PDF文件第8页浏览型号MAX3881ECB+TD的Datasheet PDF文件第9页 
+3.3V, 2.488Gbps, SDH/SONET  
1:16 Deserializer with Clock Recovery  
PHADJ+ PHADJ-  
FIL+ FIL-  
V
CC  
50  
Q
D
SDI+  
SDI-  
PD15  
PECL  
CK  
AMP  
0
I
16-BIT  
DEMULTIPLEXER  
MUX  
PHASE &  
FREQUENCY  
DETECTOR  
LOOP  
FILTER  
VCO  
SLBI+  
SLBI-  
0
I
AMP  
PD1  
PD0  
PECL  
PECL  
50Ω  
V
CC  
SIS  
MAX3881  
PCLK+  
PCLK-  
CLOCK  
DIVIDER  
PECL  
TTL  
LOL  
Figure 3. MAX3881 Functional Diagram  
dissipation by using a differential signal architecture  
and low-noise design techniques. The PLL recovers the  
serial clock from the serial input data stream. The  
demultiplexer generates a 16-bit-wide 155Mbps paral-  
lel data output.  
Detailed Description  
The MAX3881 deserializer with clock recovery converts  
2.488Gbps serial data to 16-bit-wide, 155Mbps parallel  
data. The device combines a fully integrated phase-  
locked loop (PLL), input amplifier, data retiming block,  
16-bit demultiplexer, clock divider, and PECL output  
buffer (Figure 3). The PLL consists of a phase/frequen-  
cy detector (PFD), a loop filter, and a voltage-controlled  
oscillator (VCO). The MAX3881 is designed to deliver  
the best combination of jitter performance and power  
Input Amplifier  
The input amplifiers on both the main data and system  
loopback accept a differential input amplitude from  
50mVp-p to 800mVp-p. The bit error ratio (BER) is bet-  
ter than 1 x 10-10 for input signals as small as 9.5mVp-p,  
6
_______________________________________________________________________________________  

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