Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> MAX3861EGG

MAX3861EGG

更新时间： 2024-02-07 07:45:18

品牌	Logo	应用领域
美信 - MAXIM		电信集成电路放大器
页数	文件大小	规格书
13页	1554K
描述
2.7Gbps Post Amp with Automatic Gain Control

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技术参数
数据手册

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MAX3861EGG 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	24
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.33.00.01	风险等级：	5.77
应用程序：	ATM;SONET	JESD-30 代码：	S-XQCC-N24
JESD-609代码：	e3	长度：	4 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	24	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	0.8 mm
标称供电电压：	3.3 V	表面贴装：	YES
技术：	BIPOLAR	电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4 mm	Base Number Matches：	1

MAX3861EGG 数据手册

2.7Gbps Post Amp with Automatic Gain Control

Detailed Description

Figure 1 is a functional diagram of the MAX3861 auto-

matic gain-control amplifier. The MAX3861 is divided

into three sections: main signal path, input signal

detection, and output signal detection.

CZ+

CZ-

OUT+

OUT-

IN+

IN-

MAIN SIGNAL PATH

Main Signal Path

The main signal path consists of variable gain ampli-

fiers with CML output levels and an offset cancellation

loop. This configuration allows for overall gains ranging

from -9.5dB to 43.5dB.

OSM

CONTROL

BLOCK

AND

OUTPUT

SIGNAL

DETECT

VREF

CG+

CG-

MAX3861

Offset-Cancellation Loop

The offset-cancellation loop partially reduces additional

offset at the input. In communications systems using

NRZ data with a 50% duty cycle, pulse-width distortion

present in the signal or generated by the transimped-

ance amplifier appears as input offset and is partially

removed by the offset cancellation loop. An external

capacitor is required between CZ+ and CZ- to com-

pensate the offset cancellation loop and determine the

lower 3dB frequency of the signal path.

CD+

CD-

RSSI

SD CIRCUITRY

GND

Input Signal Detection and

SD Circuitry

The input signal detection circuitry consists of variable

gain amplifiers and threshold voltages. Input signal

detection information is compared to an internal refer-

ence and creates the RSSI voltage and an internal ref-

erence signal. The signal detect (SD) circuitry indicates

when the input signal is below the programmed thresh-

old by comparing a voltage proportional to the RSSI

signal with internally generated control voltages. The

SD threshold is set by a control voltage developed

Figure 1. Functional Diagram

Output Signal Monitor and

Amplitude Control

Output amplitude typically can be adjusted from

400mV

to 920mV

by applying a control voltage

P-P

(0V to 2.0V) to the SC pin. See Output Signal Amplitude

vs. SC Pin Voltage in the Typical Operating

Characteristics. Connect the VREF pin (2.0V) to the SC

pin for maximum output amplitude. The output signal

monitor pin provides a DC voltage that is linearly pro-

portional to the output signal.

across the external TH resistor (R ). Two control volt-

ages, V

and V

, define the signal

ASSERT

DEASSERT

detect assert and deassert levels. To prevent SD chat-

ter in the region of the programmed threshold, 2.8dB to

6.3dB of hysteresis is built into the SD assert/deassert

function and thus, once asserted, SD is not deasserted

until sufficient gain is retained. When input signal

detection (SD and RSSI) is not required, tie EN to a TTL

low to power-down this circuitry.

Design Procedure

Program the SD Threshold

The SD threshold is programmed by an external resis-

tor, R , between the range of 2mV

to 100mV

P-P

The circuit is designed to have approximately 4.5dB of

hysteresis over the full range. See Signal Detect

Threshold vs. R

graph in the Typical Operating

Characteristics for proper sizing.

_______________________________________________________________________________________

1...4 5 678 9 10...13

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