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MAX3748AETE

更新时间： 2024-02-05 07:15:52
品牌 Logo 应用领域
美信 - MAXIM ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路放大器异步传输模式
页数 文件大小 规格书
11页 415K
描述
Compact 155Mbps to 3.2Gbps Limiting Amplifier

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MAX3748AETE 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFN
包装说明：HVQCCN, LCC16,.12SQ,20针数：16
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.42应用程序：ATM;SONET
JESD-30 代码：S-XQCC-N16JESD-609代码：e0
长度：3 mm功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC16,.12SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not Qualified座面最大高度：0.8 mm
子类别：ATM/SONET/SDH ICs最大压摆率：0.049 mA
标称供电电压：3.3 V表面贴装：YES
技术：BIPOLAR电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3 mmBase Number Matches：1

MAX3748AETE 数据手册

 浏览型号MAX3748AETE的Datasheet PDF文件第4页浏览型号MAX3748AETE的Datasheet PDF文件第5页浏览型号MAX3748AETE的Datasheet PDF文件第6页浏览型号MAX3748AETE的Datasheet PDF文件第8页浏览型号MAX3748AETE的Datasheet PDF文件第9页浏览型号MAX3748AETE的Datasheet PDF文件第10页 
Compact 155Mbps to 3.2Gbps  
Limiting Amplifier  
V
IN  
V
CC  
SIGNAL ON  
1dB  
6dB  
MAX DEASSERT LEVEL  
0.25pF  
50  
50  
IN+  
IN-  
POWER-DETECT WINDOW  
MIN DEASSERT LEVEL  
75k  
0.25pF  
ESD  
STRUCTURES  
SIGNAL OFF  
TIME  
0V  
Figure 2. LOS Deassert Threshold Set 1dB Below the Minimum  
by Receiver Sensitivity (for Selected R  
Figure 3. CML Input Buffer  
)
TH  
Offset Correction Loop  
The MAX3748/MAX3748A is susceptible to DC offsets  
in the signal path because it has high gain. In commu-  
nication systems using NRZ data with a 50% duty  
cycle, pulse-width distortion present in the signal or  
generated in the transimpedance amplifier appears as  
an input offset and is reduced by the offset correction  
loop. For Gigabit Ethernet and Fibre Channel applica-  
tions, no capacitor is required. For SONET applications,  
V
CC  
50  
50  
OUT+  
OUT-  
Q3  
Q4  
Q1  
Q2  
ESD  
STRUCTURES  
C
= 0.1µF is recommended. This capacitor deter-  
AZ  
DISABLE  
DATA  
mines the lower 3dB frequency of the data path.  
CML Output Buffer  
18mA  
18mA  
The MAX3748/MAX3748A limiting amplifier’s CML out-  
put provides high tolerance to impedance mismatches  
and inductive connectors. The output current is approx-  
imately 18mA. The output is disabled by connecting the  
DISABLE  
DISABLE  
DISABLE pin to V . If the LOS pin is connected to the  
CC  
DISABLE pin, the outputs OUT+ and OUT- are at a stat-  
ic voltage (squelch) whenever the input signal level  
drops below the LOS threshold. The output buffer can  
be AC- or DC-coupled to the load (Figure 4).  
Figure 4. CML Output Buffer  
deassert levels. To prevent LOS chatter in the region of  
the programmed threshold, approximately 2dB of hys-  
teresis is built into the LOS assert/deassert function.  
Once asserted, LOS is not deasserted until the input  
amplitude rises to the required level (V  
(Figure 5).  
Power-Detect and  
Loss-of-Signal Indicator  
)
The MAX3748/MAX3748A is equipped with an LOS cir-  
cuitry, which indicates when the input signal is below a  
DEASSERT  
programmable threshold, set by resistor R at the TH  
TH  
Design Procedure  
pin (see Typical Operating Characteristics for appropri-  
ate resistor sizing). An averaging peak-power detector  
compares the input signal amplitude with this threshold  
and feeds the signal detect information to the LOS out-  
put, which is open collector. Two control voltages,  
Program the LOS Assert Threshold  
External resistor R programs the LOS threshold. See  
TH  
the Assert/Deassert Levels vs. R graph in the Typical  
TH  
Operating Characteristics to select the appropriate  
V
and V  
, define the LOS assert and  
DEASSERT  
ASSERT  
resistor.  
________________________________________________________________________________________  
7
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