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MAX3679A PDF预览

MAX3679A

更新时间： 2024-01-16 21:00:43
品牌 Logo 应用领域
美信 - MAXIM 晶体时钟发生器
页数 文件大小 规格书
11页 387K
描述
+3.3V, Low-Jitter Crystal to LVPECL Clock Generator

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MAX3679A 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred包装说明：QCCN, LCC32,.2SQ,20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.52
JESD-30 代码：S-PQCC-N32JESD-609代码：e3
湿度敏感等级：1端子数量：32
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QCCN
封装等效代码：LCC32,.2SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：225
电源：3.3 V认证状态：Not Qualified
子类别：Clock Generators最大压摆率：100 mA
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIEDuPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHER
Base Number Matches：1

MAX3679A 数据手册

 浏览型号MAX3679A的Datasheet PDF文件第3页浏览型号MAX3679A的Datasheet PDF文件第4页浏览型号MAX3679A的Datasheet PDF文件第5页浏览型号MAX3679A的Datasheet PDF文件第7页浏览型号MAX3679A的Datasheet PDF文件第8页浏览型号MAX3679A的Datasheet PDF文件第9页 
+3.3V, Low-Jitter Crystal to LVPECL  
Clock Generator  
Pin Description  
PIN  
1
NAME  
FUNCTION  
Power Supply for QB0 and QB1 Clock Outputs. Connect to +3.3V.  
Supply Ground  
V
CCO_B  
2, 19, 24  
GND  
LVCMOS/LVTTL Input. Enables/disables QB0 clock output. Connect pin high to enable LVPECL  
clock output QB0. Connect low to set QB0 to a logic 0. Has internal 50kꢀ input impedance.  
3
4, 5  
6
QB0_OE  
SELB1,  
SELB0  
LVCMOS/LVTTL Input. Controls NB divider setting. Has 50kꢀ input impedance. See Table 2 for  
more information.  
MX3679A  
LVCMOS/LVTTL Input. Enables/disables QA_C clock output. Connect pin high to enable QA_C.  
QAC_OE  
MR  
Connect low to set QA_C to a high-impedance state. Has internal 75kꢀ pullup to V  
.
CC  
LVCMOS/LVTTL Input. Master reset input. Pulse high for > 1μs to reset all dividers. Has internal  
75kꢀ pulldown to GND. Not required for normal operation.  
7
8
GNDO_A  
QA_C  
Ground for QA_C Output. Connect to supply ground.  
LVCMOS Clock Output  
9
10  
11  
12  
13  
V
V
Power Supply for QA_C Clock Output. Connect to +3.3V.  
Power Supply for QA Clock Output. Connect to +3.3V.  
Noninverting Clock Output, LVPECL  
DDO_A  
CCO_A  
QA  
QA  
Inverting Clock Output, LVPECL  
LVCMOS/LVTTL Input (Active Low). Connect low to bypass the internal PLL. Connect high for  
normal operation. When in bypass mode the output dividers are set to divide by 1. Has internal  
14  
BYPASS  
75kꢀ pullup to V  
.
CC  
15  
16  
RES1  
RES0  
Not Internally Connected. Connect to GND, V , or leave open for normal operation.  
CC  
Reserved for Test. Connect to GND for normal operation.  
Analog Power Supply for the VCO. Connect to +3.3V. For additional power-supply noise filtering,  
17  
18  
20  
V
CCA  
this pin can connect to V through 10.5ꢀ as shown in Figure 2 (requires V = +3.3V 5%).  
CC  
CC  
V
CC  
Core Power Supply. Connect to +3.3V.  
LVCMOS/LVTTL Input. Enables/disables the QA clock output. Connect this pin high to enable the  
LVPECL clock output QA. Connect low to set QA to a logic 0. Has internal 75kꢀ pullup to V  
QA_OE  
.
CC  
SELA0,  
SELA1  
LVCMOS/LVTTL Input. Controls NA divider setting. See Table 2 for more information. Has 50kꢀ  
input impedance.  
21, 22  
23  
LVCMOS/LVTTL Input. Enables/disables QB1 clock output. Connect pin high to enable LVPECL  
clock output QB1. Connect low to set QB1 to a logic 0. Has internal 50kꢀ input impedance.  
QB1_OE  
25  
26  
27  
X_OUT  
X_IN  
Crystal Oscillator Output  
Crystal Oscillator Input  
REF_IN  
LVCMOS Reference Clock Input. Self-biased to allow AC- or DC-coupling.  
LVCMOS/LVTTL Input. Connect high or leave open to use a crystal. Connect low to use REF_IN.  
28  
IN_SEL  
Has internal 75kꢀ pullup to V  
.
CC  
29  
30  
31  
32  
—
QB1  
QB1  
QB0  
QB0  
EP  
LVPECL, Inverting Clock Output  
LVPECL, Noninverting Clock Output  
LVPECL, Inverting Clock Output  
LVPECL, Noninverting Clock Output  
Exposed Pad. Connect to supply ground for proper electrical and thermal performance.  
6
_______________________________________________________________________________________  
1...3456789...11

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