MAX2605–MAX2609
45MHz to 650MHz, Integrated IF
VCOs with Differential Output
the cathode of the varactor. This is accomplished
through the use of a simple bypass capacitor connect-
ed from TUNE to ground. The value of this capacitor
should be greater than or equal to the values listed in
Table 2.
from OUT- and OUT+ (in place of resistors) to V
provide DC bias for the output stage. The series capac-
itors are connected from OUT- and OUT+ to the load.
to
CC
The values for L
(Z and Z ) and C
(C
MATCH 1
MATCH
1
2
and C ) are chosen according to the operating fre-
2
quency and load impedance. As the output stage is
essentially a high-speed current switch, traditional lin-
ear impedance using techniques with [S] parameters
do not apply. To achieve a reactive power match, start
with the component values provided in the EV kit, and
adꢀust values experimentally.
This capacitor provides an AC “short” to ground for the
internal node of the varactor. It is acceptable to select
the next-largest standard-value capacitor. Use a
capacitor with a low-loss dielectric such as NPO; X7R-
based capacitors are not suitable. Omitting this capac-
itor would affect the tuning characteristics of the
MAX2605–MAX2609. Proper operation of the VCOs
requires the use of this bypass capacitor.
In general, the differential output may be applied in any
manner, as would conventional differential outputs. The
only constraints are the need for a pull-up element to
The MAX2605–MAX2609 VCO is designed to tune over
the full tuning range with a voltage range of 0.4V to
2.4V applied to TUNE. This voltage typically originates
from the output of the phase-locked (PLL) loop filter.
V
and a voltage swing limit at the output pins OUT-
CC
and OUT+.
Layout Considerations
In general, a properly designed PC board is essential
to any RF/microwave circuit or system. Always use con-
trolled impedance lines (microstrip, coplanar wave-
guide, etc.) on high-frequency signals. Always place
Output Interface
The MAX2605–MAX2609 VCO includes a differential
output amplifier after the oscillator core. The amplifier
stage provides valuable isolation and offers a flexible
interface to the IF stages, such as a mixer and PLL
prescaler. The output can be taken single ended or dif-
ferentially; however, the maximum output power and
lowest harmonic output are achieved in the differential
output mode.
decoupling capacitors as close to the V
pin as pos-
CC
sible. For low phase noise and spurious content, use an
appropriate size decoupling capacitor. For long V
CC
lines, it may be necessary to add additional decoupling
capacitors located further from the device. Always pro-
vide a low-inductance path to ground. Keep the GND
vias as close to the device as possible. In addition, the
VCO should be placed as far away from the noisy sec-
tion of a larger system, such as a switching regulator or
digital circuits. Use star topology to separate the
ground returns.
Both outputs (OUT- and OUT+) are open-collector
types and require a pull-up element to V ; this can be
CC
either resistive or inductive. A resistor pull-up is the
most straightforward method of interfacing to the out-
put, and works well in applications that operate at lower
frequencies or only require a modest voltage swing.
The resonator tank circuit (L ) is critical in determining
F
In Figure 6, Z1 and Z2 are 1kΩ pull-up resistors that are
connected from OUT+ and OUT- to V , respectively.
CC
the VCO’s performance. For best performance, use
high-Q components and choose values carefully. To
minimize the effects of parasitic elements, which
These resistors provide DC bias for the output amplifier
and are the maximum value permitted with compliance
to the output voltage swing limits. In addition, the 1kΩ
resistors maximize the swing at the load. DC-blocking
capacitors are connected from OUT- and OUT+ to the
load. If the load driven is primarily resistive and the
VCO operating frequency is below the -3dB bandwidth
of the output network, then the peak-to-peak differential
signal amplitude is approximately:
degrade circuit performance, place L and C
close
F
BYP
to their respective pins. Specifically, place C
ly across pins 2 (GND) and 3 (TUNE).
direct-
BYP
For the higher frequency versions, consider the extra
parasitic inductance and capacitance when determin-
ing the oscillation frequency. Be sure to account for the
following: PC board pad capacitance at IND, PC board
pad capacitance at the ꢀunction of two series inductors,
series inductance of any PC board traces, and the
inductance in the ground return path from the ground-
ed side of the inductor and IC’s GND pin. For best
results, connect the “ground” side to the tuning induc-
tor as close to pin 2 as possible. In addition, remove
1kΩ × R
LOAD
V
diff = 2 × 1mA
OUTp−p
1kΩ + R
LOAD
To optimize the output voltage swing or the output
power, use a reactive power match. The matching net-
work is a simple shunt-inductor series-capacitor circuit,
as shown in Figure 6. The inductors are connected
the ground plane around and under L and C
F
minimize the effects of parasitic capacitance.
to
BYP
12
Maxim Integrated
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