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MAX109EHF-D

更新时间： 2024-10-01 03:14:27
品牌 Logo 应用领域
美信 - MAXIM 放大器
页数 文件大小 规格书
29页 436K
描述
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs

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MAX109EHF-D 数据手册

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19-0795; Rev 0; 4/07  
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier  
and 1:4 Demultiplexed LVDS Outputs  
MAX109  
General Description  
Features  
The MAX109, 2.2Gsps, 8-bit, analog-to-digital converter  
(ADC) enables the accurate digitizing of analog signals  
with frequencies up to 2.5GHz. Fabricated on an  
advanced SiGe process, the MAX109 integrates a high-  
performance track/hold (T/H) amplifier, a quantizer, and  
a 1:4 demultiplexer on a single monolithic die. The  
MAX109 also features adjustable offset, full-scale volt-  
age (via REFIN), and sampling instance allowing multi-  
ple ADCs to be interleaved in time.  
♦ Ultra-High-Speed, 8-Bit, 2.2Gsps ADC  
♦ 2.8GHz Full-Power Analog Input Bandwidth  
♦ Excellent Signal-to-Noise Performance  
44.6dB SNR at f = 300MHz  
IN  
44dB SNR at f = 1600MHz  
IN  
♦ Superior Dynamic Range at High-IF  
61.7dBc SFDR at f = 300MHz  
IN  
50.3dBc SFDR at f = 1600MHz  
IN  
The innovative design of the internal T/H amplifier,  
which has a wide 2.8GHz full-power bandwidth,  
enables a flat-frequency response through the second  
Nyquist region. This results in excellent ENOB perfor-  
mance of 6.9 bits. A fully differential comparator design  
and decoding circuitry reduce out-of-sequence code  
errors (thermometer bubbles or sparkle codes) and  
provide excellent metastability performance (1014 clock  
cycles). This design guarantees no missing codes.  
-60dBc IM3 at f  
= 1590MHz and f  
= 1610MHz  
IN1  
IN2  
♦ 500mV  
Differential Analog Inputs  
P-P  
♦ 6.8W Typical Power Including the Demultiplexer  
♦ Adjustable Range for Offset, Full-Scale, and  
Sampling Instance  
♦ 50Ω Differential Analog Inputs  
♦ 1:4 Demultiplexed LVDS Outputs  
The analog input is designed for both differential and  
single-ended use with a 500mV  
input-voltage range.  
P-P  
♦ Interfaces Directly to Common FPGAs with DDR  
The output data is in standard LVDS format, and is  
demultiplexed by an internal 1:4 demultiplexer. The  
LVDS outputs operate from a supply-voltage range of  
3V to 3.6V for compatibility with single 3V-reference  
systems. Control inputs are provided for interleaving  
additional MAX109 devices to increase the effective  
system-sampling rate.  
and QDR Modes  
Ordering Information  
PIN-  
PACKAGE  
PKG  
CODE  
PART  
TEMP RANGE  
MAX109EHF-D  
D = Dry pack.  
-40°C to +85°C  
256 SBGA  
H256-1  
The MAX109 is offered in a 256-pin Super Ball-Grid Array  
(SBGA) package and is specified over the extended  
industrial temperature range (-40°C to +85°C).  
Pin Configuration  
Applications  
Radar Warning Receivers (RWR)  
TOP VIEW  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20  
Light Detection and Ranging (LIDAR)  
Digital RF/IF Signal Processing  
Electronic Warfare (EW) Systems  
High-Speed Data-Acquisition Systems  
Digital Oscilloscopes  
A
B
C
D
E
F
G
H
J
MAX109  
256-PIN  
High-Energy Physics Instrumentation  
ATE Systems  
K
L
SBGA PACKAGE  
M
N
P
R
T
U
V
W
Y
256-PIN SUPER BALL-GRID ARRAY  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at  
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  
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MAX109EHF-D 替代型号

型号 品牌 替代类型 描述 数据表
MAX109EHF-TD MAXIM

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