Datasheet > M80C51FB

M80C51FB

更新时间： 2022-11-26 15:35:33

品牌	Logo	应用领域
英特尔 - INTEL		微控制器
页数	文件大小	规格书
12页	186K
描述
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

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M80C51FB 数据手册

M80C51FB

D.C. CHARACTERISTICS: (Over Specified Operating Conditions) (Continued)

Symbol

Parameter

Min

Max

Unit

Test Conditions

e b

OH1

Output High Voltage

(Port 0 in External Bus Mode,

ALE, PSEN)

0.3

0.7

1.5

200 mA (Note 2)

3.2 mA

7.0 mA (Note 4)

0.45V

Logical 0 Input Current

(Ports 1, 2, and 3)

Input leakage Current (Port 0)

0.45V

Logical 1 to 0 Transition Current

(Ports 1, 2, and 3)

750

RRST

CIO

RST Pulldown Resistor

Pin Capacitance

225

1 MHz, 25 C

Power Supply Current:

Active Mode 16 MHz

Idle Mode 16 MHz

(Note 3)

Power Down Mode 16 MHz

130

NOTES:

1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V s of ALE and Ports

1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to

0 transitions during bus operations. In applications where capacitance loading exceeds 100 pFs, the noise pulse on the ALE

signal may exceed 0.8V. In these cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an Address Latch

with a Schmitt Trigger Strobe input.

2. Capacitive loading on Ports 0 and 2 cause the V

the address lines are stabilizing.

on ALE and PSEN to drop below the V

0.3 specification when

3. See Figures 5–8 for load circuits. Minimum V

for Power Down is 2V.

4. Care must be taken not to exceed the maximum allowable power dissipation.

5. Under steady state (non-transient) conditions, I must be externally limited as follows:

Maximum I per port pin:

10mA

Maximum I per 8-bit portÐ

Port 0:

Ports 1, 2 and 3:

Maximum total I for all output pins:

26 mA

15 mA

71 mA

If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater

OL OL

than the listed test conditions.

271172–6

271172–7

All other pins disconnected

TCHCL 5 ns

TCLCH

TCHCL

5 ns

TCLCH

Figure 5. I Load Circuit Active Mode

Figure 6. I Load Circuit Idle Mode

1...4 5 678 9 10...12

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