Datasheet > 存储 > SRAM> M5M532R16TP-15

M5M532R16TP-15

更新时间： 2024-02-29 20:10:17

品牌	Logo	应用领域
三菱 - MITSUBISHI		存储内存集成电路静态存储器光电二极管
页数	文件大小	规格书
8页	77K
描述
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM

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数据手册

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M5M532R16TP-15 技术参数

生命周期：	Obsolete	零件包装代码：	TSOP2
包装说明：	SOP,	针数：	44
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.84
Is Samacsys：	N	最长访问时间：	15 ns
JESD-30 代码：	R-PDSO-G44	内存密度：	524288 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	16
功能数量：	1	端子数量：	44
字数：	32768 words	字数代码：	32000
组织：	32KX16	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	认证状态：	Not Qualified
表面贴装：	YES	技术：	CMOS
端子形式：	GULL WING	端子位置：	DUAL
Base Number Matches：	1

M5M532R16TP-15 数据手册

MITSUBISHI LSIs

1997.01.22

M5M532R16J,TP-10,-12,-15

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM

DESCRIPTION

PIN CONFIGURATION (TOP VIEW)

The M5M532R16 is a family of 32768-word by 16-bit

static RAMs, fabricated with the high performance CMOS

process and designed for high speed application. These

devices operate on a single 5V supply, and are directly

TTL compatible.

N.C

ADDRESS

INPUTS

ADDRESS

INPUTS

OUTPUT

ENABLE

BYTE

CONTROL

INPUTS

/OE

/UB

They include a power down feature as well. In write

and read cycles, the lower and upper bytes are able

to be controled either togethe or separately by /LB

and /UB.

CHIP

SELECT

INPUTS

DQ1

DQ2

/LB

DQ16

DATA

INPUTS/

OUTPUTS

DATA

INPUTS/

DQ15

DQ3

DQ4

DQ14 OUTPUTS

DQ13

(5V) Vcc

(0V) GND

DQ5

GND (0V)

Vcc (5V)

DQ12

FEATURES

Fast access time M5M532R16J,TP-10

10ns(max)

12ns(max)

15ns(max)

500mW(typ)

15mW(typ)

M5M532R16J,TP-12

DATA

DQ6

DQ11

INPUTS/

M5M532R16J,TP-15

OUTPUTS

DQ7

DQ8

DQ10 OUTPUTS

DQ9

Low power dissipation Active

Stand by

WRITE

CONTROL

INPUT

A14

A13

A12

A11

Single +5V power supply

ADDRESS

INPUTS

ADDRESS

INPUTS

Fully static operation : No clocks, No refresh

Common data I/O

A10

Easy memory expansion by /S

Three-state outputs : OR-tie capability

OE prevents data contention in the I/O bus

Directly TTL compatible : All inputs and outputs

Separate control of lower and upper bytes by /LB and /UB

Outline 44P0K(J)

44P3W-H(TP)

PACKAGE

APPLICATION

High-speed memory system

M5M532R16J : 44pin 400mil SOJ

M5M532R16VP: 44pin 400mil TSOP(II)

FUNCTION

When setting /LB at a high level and other pins are in

an active state, upper-Byte are in a selectable mode

in which both reading and writing are enable, and

lower-Byte are in a non-selectable mode. And when

setting /UB at a high level and other pins are in an

active state, lower-Byte are in a selectable mode in

which both reading and writing are enable, and

upper-Byte are in a non-selectable mode.

The operation mode of the M5M532R16 is determined

by a combination of the device control inputs /S, /W,

/OE, /LB, and /UB. Each mode is summarized in the

function table.

A write cycle is executed whenever the low level /W

overlaps with low level /LB and/or low level /UB and low

level /S. The address must be set-up before write cycle

and must be stable during the entire cycle.

When setting /LB and /UB at a high level or /S at high

level, the chip is in a non-selectable mode in which

both reading and writing are disabled. In this mode,

the output stage is in a high-impedance state,

allowing OR-tie with other chips and memory

expansion by /LB, /UB and /S.

Signal-/S controls the power-down feature. When /S

goes high, power dissapation is reduced extremely.

The access time from /S is equivalent to the address

access time.

The data is latched into a cell on the traling edge of

/W, /LB, /UB or /S, whichever occurs first, requiring the

set-up and hold time relative to these edge to be

maintained. The output enable input /OE directly

controls the output stage. Setting the /OE at a high

level, the output stage is in a high impedance state, and

the data bus contention problem in the write cycle is

eliminated.

A read cycle is excuted by setting W at a high level

and /OE at a low level while /LB and/or /UB and /S are

in an active state. (/LB and/or /UB=L, /S=L)

MITSUBISHI

ELECTRIC

12 3 4 5 6 7 8

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