Datasheet > 可编程逻辑 > 可编程逻辑器件> M5-192/104-10YC

M5-192/104-10YC

更新时间： 2024-01-28 15:16:12

品牌	Logo	应用领域
莱迪思 - LATTICE		可编程逻辑器件输入元件时钟
页数	文件大小	规格书
47页	1092K
描述
Fifth Generation MACH Architecture

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技术参数
数据手册

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M5-192/104-10YC 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
Reach Compliance Code：	unknown	风险等级：	5.72
Is Samacsys：	N	其他特性：	YES
最大时钟频率：	83 MHz	系统内可编程：	YES
JESD-30 代码：	S-PQFP-G144	JESD-609代码：	e0
JTAG BST：	YES	专用输入次数：
I/O 线路数量：	104	宏单元数：	192
端子数量：	144	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	0 DEDICATED INPUTS, 104 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP144,1.2SQ
封装形状：	SQUARE	封装形式：	FLATPACK
电源：	5 V	可编程逻辑类型：	EE PLD
传播延迟：	16 ns	认证状态：	Not Qualified
子类别：	Programmable Logic Devices	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	QUAD	Base Number Matches：	1

M5-192/104-10YC 数据手册

Macrocells

The macrocells for MACH 5 devices consist of a storage element which can be conﬁgured for

combinatorial, registered or latched operation (Figure 3). The D-type ﬂip-ﬂops can be conﬁgured

as T-type, J-K, or S-R operation through the use of the XOR gate associated with each macrocell.

Each PAL block has the capability to provide two input registers by using macrocells 0 and 15. In

order to use this option, these macrocells must be accessed via the I/O pins associated with

macrocells 3 and 12, respectively. Once the macrocell is used as an input register, it cannot be used

for logic, so its clusters can be re-directed through the logic allocator to another macrocell. The

I/O pins associated with macrocells 0 and 15 can still be used as input pins. Although the I/O pins

for macrocells 3 and 12 are used to connect to the input registers, these macrocells can still be

used as “buried” macrocells to drive device logic via the matrix.

Macrocell

Logic

Allocator

5-8

Clusters/

Prog. Polarity

Mode

Selection

20446G-003

Figure 3. Macrocell Diagram

Control Generator

The control generator provides four conﬁgurable clock lines and three conﬁgurable set/reset lines to

each macrocell in a PAL block. Any of the four clock lines and any of the three set/reset lines can

be independently selected by any ﬂip-ﬂop within a block. The clock lines can be conﬁgured to

provide synchronous global (pin) clocks and asynchronous product term clocks, sum term clocks,

and latch enables (Figure 4). Three of the four global clocks, as well as two product-term clocks

and one sum-term clock, are available per PAL block. Positive or negative edge clocking is

available as well as advanced clocking features such as complementary and biphase clocking.

Complementary clocking provides two clock lines exactly 180 degrees out of phase, and is useful

in applications such as fast data paths. A biphase clock line clocks ﬂip-ﬂops on both the positive

and negative edges of the clock. The conﬁguration options for the four clock lines per PAL block

are as follows:

Clock Line 0 Options

Global clock (0, 1, 2, or 3) with positive or negative edge clock enable

Product-term clock (A*B*C)

Sum-term clock (A+B+C)

MACH 5 Family

1...3 4 567 8 9...47

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与M5-192/104-10YC相关器件

型号	品牌	描述	获取价格	数据表
M5-192/104-10YI	LATTICE	Fifth Generation MACH Architecture	获取价格
M5-192/104-12AC	LATTICE	Fifth Generation MACH Architecture	获取价格
M5-192/104-12AI	LATTICE	Fifth Generation MACH Architecture	获取价格
M5-192/104-12HC	LATTICE	Fifth Generation MACH Architecture	获取价格
M5-192/104-12HI	LATTICE	Fifth Generation MACH Architecture	获取价格
M5-192/104-12VC	LATTICE	Fifth Generation MACH Architecture	获取价格

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