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M38510/66302BEA

更新时间： 2024-09-28 11:07:59
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德州仪器 - TI 计数器
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14页 203K
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同步 4 位二进制计数器 | J | 16 | -55 to 125

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M38510/66302BEA 数据手册

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SN54HC161, SN74HC161  
4-BIT SYNCHRONOUS BINARY COUNTERS  
SCLS297A – JANUARY 1996 – REVISED MAY 1997  
SN54HC161 . . . J OR W PACKAGE  
SN74HC161 . . . D OR N PACKAGE  
(TOP VIEW)  
Internal Look-Ahead for Fast Counting  
Carry Output for n-Bit Cascading  
Synchronous Counting  
CLR  
CLK  
A
V
CC  
RCO  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Synchronously Programmable  
Package Options Include Plastic  
Small-Outline (D) and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
Q
A
B
C
D
Q
B
Q
C
Q
D
ENT  
ENP  
GND  
LOAD  
description  
These synchronous, presettable counters feature  
an internal carry look-ahead for application in  
high-speed counting designs. The ’HC161 are  
4-bit binary counters. Synchronous operation is  
provided by having all flip-flops clocked  
simultaneously so that the outputs change  
coincident with each other when so instructed by  
the count-enable (ENP, ENT) inputs and internal  
gating. This mode of operation eliminates the  
output counting spikes that are normally  
associated with synchronous (ripple-clock)  
counters. A buffered clock (CLK) input triggers the  
four flip-flops on the rising (positive-going) edge of  
the clock waveform.  
SN54HC161 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
A
B
Q
Q
4
5
6
7
8
A
B
17  
16  
15  
14  
NC  
C
NC  
Q
Q
C
D
D
9 10 11 12 13  
These counters are fully programmable; that is,  
they can be preset to any number between 0 and  
9 or 15. As presetting is synchronous, setting up  
a low level at the load input disables the counter  
and causes the outputs to agree with the setup  
data after the next clock pulse, regardless of the  
levels of the enable inputs.  
NC – No internal connection  
The clear function for the ’HC161 is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop  
outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.  
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without  
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).  
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a  
high-level pulse while the count is maximum (9 or 15 with Q high). This high-level overflow ripple-carry pulse  
A
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the  
level of CLK.  
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that  
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of  
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the  
stable setup and hold times.  
The SN54HC161 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74HC161 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

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M38510/66302BEA 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC161M96 TI

完全替代

 High-Speed CMOS Logic Presettable Counters
CD74HC161M TI

完全替代

 High Speed CMOS Logic Presettable Counters
CD74HC161E TI

完全替代

 High Speed CMOS Logic Presettable Counters

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