Datasheet > M381L3223FUM-CAA

M381L3223FUM-CAA

更新时间： 2023-01-03 03:59:31

品牌	Logo	应用领域
三星 - SAMSUNG		动态存储器双倍数据速率
页数	文件大小	规格书
25页	487K
描述
DDR DRAM Module, 32MX72, 0.75ns, CMOS, DIMM-184

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数据手册

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M381L3223FUM-CAA 数据手册

256MB, 512MB Unbuffered DIMM Pb-Free

DDR SDRAM

184Pin Unbuffered DIMM based on 256Mb F-die (x8, x16)

Ordering Information

Part Number

Density

128MB

256MB

512MB

Organization

16M x 64

32M x 64

32M x 72

64M x 64

64M x 72

Component Composition

Height

1,250mil

M368L1624FUM-C(L)B3/AA/A2/B0

M368L3223FUN-C(L)B3/AA/A2/B0

M381L3223FUM-C(L)B3/AA/A2/B0

M368L6423FUN-C(L)B3/AA/A2/B0

M381L6423FUM-C(L)B3/AA/A2/B0

16Mx16 (K4H561638F) * 4EA

32Mx8 (K4H560838F) * 8EA

32Mx8 (K4H560838F) * 9EA

32Mx8 (K4H560838F) * 16EA

32Mx8 (K4H560838F) * 18EA

Operating Frequencies

B3(DDR333@CL=2.5)

AA(DDR266@CL=2)

133MHz

A2(DDR266@CL=2)

133MHz

B0(DDR266@CL=2.5)

100MHz

Speed @CL2

Speed @CL2.5

CL-tRCD-tRP

133MHz

166MHz

2.5-3-3

133MHz

2-2-2

2-3-3

2.5-3-3

Feature

• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency 2, 2.5 (clock)

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

• Serial presence detect with EEPROM

• PCB : Height 1,250 (mil), single (128MB, 256MB), double (512MB) sided

•SSTL_2 Interface Pb-Free

• RoHS compliant

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Revision 1.2 Oct. 2004

1 234 5 6 7...25

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M381L3223FUM-LB0	SAMSUNG	DDR DRAM Module, 32MX72, 0.75ns, CMOS, DIMM-184	获取价格
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