PC100 Unbuffered DIMM
M366S3253ATS
M366S3253ATS SDRAM DIMM
32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
FEATURE
The Samsung M366S3253ATS is a 32M bit x 64 Synchronous
Dynamic RAM high density memory module. The Samsung
M366S3253ATS consists of eight CMOS 32M x 8 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and a
2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy
substrate. One 0.1uF and one 0.33uF decoupling capacitors are
mounted on the printed circuit board in parallel for each SDRAM.
The M366S3253ATS is a Dual In-line Memory Module and is
intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth,
high performance memory system applications.
• Performance range
Part No.
Max Freq. (Speed)
125MHz (8ns @ CL=3)
100MHz (10ns @ CL=2)
100MHz (10ns @ CL=3)
M366S3253ATS-C80
M366S3253ATS-C1H
M366S3253ATS-C1L
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB : Height (1,375mil), single sided component
PIN CONFIGURATIONS (Front side/back side)
PIN NAMES
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
Pin Name
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
CLK0, CLK2
CKE0
Function
Address input (Multiplexed)
Select bank
1
2
3
4
5
6
7
8
9
VSS
29 DQM1 57 DQ18 85
VSS 113 DQM5 141 DQ50
58
59
60
61
62
DQ0 30
DQ1 31
DQ2 32
DQ3 33
CS0
DU
VSS
A0
DQ19 86 DQ32 114 *CS1 142 DQ51
Data input/output
Clock input
VDD
87 DQ33 115 RAS 143 VDD
DQ20 88 DQ34 116 VSS 144 DQ52
NC
*VREF 90
89 DQ35 117
VDD 118
A1
A3
A5
A7
A9
145 NC
146 *VREF
147 NC
148 VSS
149 DQ53
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
VDD
34
A2
CS0, CS2
RAS
DQ4 35
DQ5 36
DQ6 37
A4
A6
A8
63 *CKE1 91 DQ36 119
64
65 DQ21 93 DQ38 121
66
VSS
92 DQ37 120
CAS
10 DQ7 38 A10/AP
DQ22 94 DQ39 122 BA0 150 DQ54
67 DQ23 95 DQ40 123 A11 151 DQ55
68
69 DQ24 97 DQ41 125 *CLK1 153 DQ56
70
71 DQ26 99 DQ43 127 VSS 155 DQ58
WE
11 DQ8 39
12 40
13 DQ9 41
BA1
VDD
VDD
DQM0 ~ 7
VDD
DQM
VSS
VSS
96
VSS 124 VDD 152 VSS
Power supply (3.3V)
Ground
14 DQ10 42 CLK0
DQ25 98 DQ42 126 A12 154 DQ57
VSS
15 DQ11 43
16 DQ12 44
17 DQ13 45
VSS
DU
CS2
*VREF
Power supply for reference
Serial data I/O
72
73
74
DQ27 100 DQ44 128 CKE0 156 DQ59
VDD 101 DQ45 129 *CS3 157 VDD
DQ28 102 VDD 130 DQM6 158 DQ60
SDA
18
VDD
46 DQM2
SCL
Serial clock
19 DQ14 47 DQM3 75 DQ29 103 DQ46 131 DQM7 159 DQ61
SA0 ~ 2
WP
Address in EEPROM
Write protection
Don¢t use
76
77 DQ31 105 *CB4 133 VDD 161 DQ63
78
79 CLK2 107 VSS 135 NC 163 *CLK3
20 DQ15 48
21 *CB0 49
22 *CB1 50
DU
VDD
NC
NC
DQ30 104 DQ47 132 *A13 160 DQ62
VSS 106 *CB5 134 NC 162 VSS
DU
23
24
25
26
27
VSS
NC
NC
VDD
WE
51
NC
No connection
80
53 *CB3 81
82
52 *CB2
NC 108 NC 136 *CB6 164 NC
WP 109 NC 137 *CB7 165 **SA0
**SDA 110 VDD 138 VSS 166 **SA1
*
These pins are not used in this module.
** These pins should be NC in the system
54
VSS
55 DQ16 83 **SCL 111 CAS 139 DQ48 167 **SA2
84
which does not support SPD.
28 DQM0 56 DQ17
VDD 112 DQM4 140 DQ49 168 VDD
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.0 Sep. 1999