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M34C02BN PDF预览

M34C02BN

更新时间: 2024-09-27 22:46:43
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
19页 149K
描述
2 Kbit Serial IC Bus EEPROM For DIMM Serial Presence Detect

M34C02BN 数据手册

 浏览型号M34C02BN的Datasheet PDF文件第2页浏览型号M34C02BN的Datasheet PDF文件第3页浏览型号M34C02BN的Datasheet PDF文件第4页浏览型号M34C02BN的Datasheet PDF文件第5页浏览型号M34C02BN的Datasheet PDF文件第6页浏览型号M34C02BN的Datasheet PDF文件第7页 
M34C02  
2 Kbit Serial I²C Bus EEPROM  
For DIMM Serial Presence Detect  
2
Two Wire I C Serial Interface  
Supports 400 kHz Protocol  
Single Supply Voltage:  
– 2.5V to 5.5V for M34C02-W  
– 2.2V to 5.5V for M34C02-L  
8
Software Data Protection for lower 128 bytes  
BYTE and PAGE WRITE (up to 16 bytes)  
RANDOM and SEQUENTIAL READ Modes  
Self-Timed Programming Cycle  
Automatic Address Incrementing  
Enhanced ESD/Latch-Up Protection  
1 Million Erase/Write Cycles (minimum)  
40 Year Data Retention (minimum)  
1
PSDIP8 (BN)  
0.25 mm frame  
8
8
1
1
DESCRIPTION  
SO8 (MN)  
150 mil width  
TSSOP8 (DW)  
169 mil width  
The M34C02 is a 2 Kbit serial EEPROM memory  
able to lock permanently the data in its first half  
(from location 00h to 7Fh). This facility has been  
designed specifically for use in DRAM DIMMs  
(dual interline memory modules) with Serial  
Presence Detect. All the information concerning  
the DRAM module configuration (such as its  
access speed, its size, its organization) can be  
kept write protected in the first half of the memory.  
Figure 1. Logic Diagram  
This bottom half of the memory area can be write-  
protected using a specially designed software  
write protection mechanism. By sending the  
device a specific sequence, the first 128 bytes of  
V
CC  
3
Table 1. Signal Names  
E0-E2  
SDA  
E0, E1, E2  
SDA  
Chip Enable Inputs  
M34C02  
SCL  
WC  
Serial Data/Address Input/  
Output  
SCL  
WC  
Serial Clock  
Write Control  
Supply Voltage  
Ground  
V
SS  
V
AI01931  
CC  
V
SS  
December 1999  
1/19  

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