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M24C01-RBN6

更新时间： 2024-02-27 03:57:47

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		存储内存集成电路光电二极管双倍数据速率可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数	文件大小	规格书
25页	451K
描述
16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM

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技术参数
数据手册

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M24C01-RBN6 技术参数

生命周期：	Obsolete	包装说明：	DIP,
Reach Compliance Code：	unknown	风险等级：	5.82
最大时钟频率 (fCLK)：	0.4 MHz	JESD-30 代码：	R-PDIP-T8
长度：	9.27 mm	内存密度：	1024 bit
内存集成电路类型：	EEPROM	内存宽度：	8
功能数量：	1	端子数量：	8
字数：	128 words	字数代码：	128
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	128X8
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
并行/串行：	SERIAL	座面最大高度：	5.33 mm
串行总线类型：	SPI	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	1.8 V	表面贴装：	NO
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	宽度：	7.62 mm
最长写入周期时间 (tWC)：	5 ms

M24C01-RBN6 数据手册

M24C16, M24C08, M24C04, M24C02, M24C01

DEVICE OPERATION

The device supports the I²C protocol. This is sum-

marized in Figure 6.. Any device that sends data

on to the bus is defined to be a transmitter, and

any device that reads the data to be a receiver.

The device that controls the data transfer is known

as the bus master, and the other as the slave de-

vice. A data transfer can only be initiated by the

bus master, which will also provide the serial clock

for synchronization. The M24Cxx device is always

a slave in all communication.

Clock (SCL), and the Serial Data (SDA) signal

must change only when Serial Clock (SCL) is driv-

en Low.

Memory Addressing

To start communication between the bus master

and the slave device, the bus master must initiate

a Start condition. Following this, the bus master

sends the Device Select Code, shown in Table 3.

(on Serial Data (SDA), most significant bit first).

The Device Select Code consists of a 4-bit Device

Type Identifier, and a 3-bit Chip Enable “Address”

(E2, E1, E0). To address the memory array, the 4-

bit Device Type Identifier is 1010b.

Start Condition

Start is identified by a falling edge of Serial Data

(SDA) while Serial Clock (SCL) is stable in the

High state. A Start condition must precede any

data transfer command. The device continuously

monitors (except during a Write cycle) Serial Data

(SDA) and Serial Clock (SCL) for a Start condition,

and will not respond unless one is given.

Each device is given a unique 3-bit code on the

Chip Enable (E0, E1, E2) inputs. When the Device

Select Code is received, the device only responds

if the Chip Enable Address is the same as the val-

ue on the Chip Enable (E0, E1, E2) inputs. How-

ever, those devices with larger memory capacities

(the M24C16, M24C08 and M24C04) need more

address bits. E0 is not available for use on devices

that need to use address line A8; E1 is not avail-

able for devices that need to use address line A9,

and E2 is not available for devices that need to use

address line A10 (see Figure 3. and Table 3. for

details). Using the E0, E1 and E2 inputs, up to

eight M24C02 (or M24C01), four M24C04, two

M24C08 or one M24C16 devices can be connect-

ed to one I²C bus. In each case, and in the hybrid

cases, this gives a total memory capacity of

16 Kbits, 2 KBytes (except where M24C01 devic-

es are used).

Stop Condition

Stop is identified by a rising edge of Serial Data

(SDA) while Serial Clock (SCL) is stable and driv-

en High. A Stop condition terminates communica-

tion between the device and the bus master. A

Read command that is followed by NoAck can be

followed by a Stop condition to force the device

into the Stand-by mode. A Stop condition at the

end of a Write command triggers the internal Write

cycle.

Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a success-

ful byte transfer. The bus transmitter, whether it be

bus master or slave device, releases Serial Data

The 8 bit is the Read/Write bit (RW). This bit is

(SDA) after sending eight bits of data. During the

set to 1 for Read and 0 for Write operations.

clock pulse period, the receiver pulls Serial

Data (SDA) Low to acknowledge the receipt of the

eight data bits.

Data Input

During data input, the device samples Serial Data

(SDA) on the rising edge of Serial Clock (SCL).

For correct device operation, Serial Data (SDA)

must be stable during the rising edge of Serial

If a match occurs on the Device Select code, the

corresponding device gives an acknowledgment

on Serial Data (SDA) during the 9 bit time. If the

device does not match the Device Select code, it

deselects itself from the bus, and goes into Stand-

by mode.

Table 4. Operating Modes

Mode

RW bit

Bytes

Initial Sequence

Current Address Read

START, Device Select, RW = 1

START, Device Select, RW = 0, Address

reSTART, Device Select, RW = 1

Similar to Current or Random Address Read

START, Device Select, RW = 0

Random Address Read

Sequential Read

Byte Write

≥ 1

V_IL

Page Write

≤16

START, Device Select, RW = 0

Note: 1. X = V_IHor V_IL.

6/25

1...3 4 567 8 9...25

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M24C01-RBN6/W	STMICROELECTRONICS	16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM	获取价格
M24C01-RBN6G	STMICROELECTRONICS	16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM	获取价格
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M24C01-RBN6G/W	STMICROELECTRONICS	16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM	获取价格
M24C01-RBN6P	STMICROELECTRONICS	16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM	获取价格

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