M2060/61/62, M2065/66/67
Integrated
Circuit
Systems, Inc.
VCSO FEC PLL FOR SONET/OTN
P r e l i m i n a r y I n f o r m a t i o n
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC
=
3.3V +
5
%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT
Ω to VCC - 2V
= 622-675MHz,
LVPECL outputs terminated with 50
Symbol Parameter
Min
Typ
Max Unit Conditions
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
10
700
700
FIN
Input Frequency
MHz
MHz
FOUT
APR
Output Frequency
FOUT0, nFOUT0, FOUT1, nFOUT
1
15
Commercial
Industrial
VCSO Absolute
Pull-Range
±120
±50
±200
±150
800
ppm
ppm
KVCO
RIN
VCO Gain
kHz/V
Wide Bandwidth
100
2100
700
Internal Loop Resistor
kΩ
PLL Loop
Constants
1
Narrow Bandwidth
kΩ
BWVCSO VCSO Bandwidth
kHz
Φn
Single Side Band
Phase Noise
1kHz Offset
10kHz Offset
100kHz Offset
-73
dBc/Hz
dBc/Hz
dBc/Hz
Fin=19.44 or
38.88 MHz
-103
-126
Mfin=32 (or 16),
Mfec=Rfec
@622.08MHz
PhaseNoise
and Jitter
0.25
0.25
50
0.5
0.5
55
J(t)
Jitter (rms)
@622.08MHz
12kHz to 20MHz
50kHz to 80MHz
P = 4, 8, or 32
ps
ps
%
2
odc
Output Duty Cycle
FOUT0, nFOUT0,
45
P = 1
40
50
60
%
FOUT1, nFOUT
1
2
200
450
500
tR
tF
Output Rise Time
ps
20% to 80%
20% to 80%
FOUT0, nFOUT0, FOUT1, nFOUT
1
2
200
450
500
Output Fall Time
ps
Table 14: AC Characteristics
Note 1: Parameters needed for PLL Simulator software; see Table 10, Example Values for Loop Filter External Components, on pg. 8.
Note 2: See Parameter Measurement Information on pg. 11.
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time
Output Duty Cycle
nFOUT
FOUT
80%
80%
VP-P
tPW
(Output Pulse Width)
20%
t
F
20%
Clock Output
t
R
tPERIOD
t
PW
odc =
t
PERIOD
Figure 7: Output Duty Cycle
Figure 6: Output Rise and Fall Time
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
11 of 12
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400