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M1AGL1000V5-FCSG281

更新时间： 2024-02-18 12:36:34

品牌	Logo	应用领域
ACTEL		栅现场可编程门阵列可编程逻辑
页数	文件大小	规格书
216页	6519K
描述
Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 108MHz, 24576-Cell, CMOS, PBGA281, 10 X 10 MM, 1.05 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, CSP-281

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M1AGL1000V5-FCSG281 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	10 X 10 MM, 1.05 MM HEIGHT, 0.50 MM PITCH, CSP-281	Reach Compliance Code：	compliant
风险等级：	5.81	Is Samacsys：	N
最大时钟频率：	108 MHz	JESD-30 代码：	S-PBGA-B281
JESD-609代码：	e0	长度：	10 mm
可配置逻辑块数量：	24576	等效关口数量：	1000000
输入次数：	215	逻辑单元数量：	24576
输出次数：	215	端子数量：	281
最高工作温度：	70 °C	最低工作温度：
组织：	24576 CLBS, 1000000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	TFBGA	封装等效代码：	BGA281,19X19,20
封装形状：	SQUARE	封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	1.5 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	1.05 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	1.575 V	最小供电电压：	1.425 V
标称供电电压：	1.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	0.5 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10 mm	Base Number Matches：	1

M1AGL1000V5-FCSG281 数据手册

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1 – IGLOO Device Family Overview

General Description

The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a

single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced

features.

The Flash*Freeze technology used in IGLOO devices enables entering and exiting an ultra-low-

power mode that consumes as little as 5 µW while retaining SRAM and register data. Flash*Freeze

technology simplifies power management through I/O and clock management with rapid recovery

to operation mode.

The Low Power Active capability (static idle) allows for ultra-low-power consumption (from 12 µW)

while the IGLOO device is completely functional in the system. This allows the IGLOO device to

control system power management based on external inputs (e.g., scanning for keyboard stimulus)

while consuming minimal power.

Nonvolatile flash technology gives IGLOO devices the advantage of being a secure, low power,

single-chip solution that is live at power-up (LAPU). IGLOO is reprogrammable and offers time-to-

market benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

IGLOO devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as

clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGL015 and

AGL030 devices have no PLL or RAM support. IGLOO devices have up to 1 million system gates,

supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.

M1 IGLOO devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM

for implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA

fabric. It has a three-stage pipeline that offers a good balance between low-power consumption

and speed when implemented in an M1 IGLOO device. The processor runs the ARMv6-M instruction

set, has a configurable nested interrupt controller, and can be implemented with or without the

debug block. Cortex-M1 is available for free from Actel for use in M1 IGLOO FPGAs.

The ARM-enabled devices have Actel ordering numbers that begin with M1AGL and do not support

AES decryption.

Flash*Freeze Technology

The IGLOO device offers unique Flash*Freeze technology, allowing the device to enter and exit

ultra-low-power Flash*Freeze mode. IGLOO devices do not need additional components to turn off

I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze

technology is combined with in-system programmability, which enables users to quickly and easily

upgrade and update their designs in the final stages of manufacturing or in the field. The ability of

IGLOO V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction

in power consumption, thus achieving the lowest total system power.

When the IGLOO device enters Flash*Freeze mode, the device automatically shuts off the clocks

and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and

data is retained.

The availability of low-power modes, combined with reprogrammability, a single-chip and single-

voltage solution, and availability of small-footprint, high pin-count packages, make IGLOO devices

the best fit for portable electronics.

v1.4

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