Datasheet > M1AGL1000V5-FFG144

M1AGL1000V5-FFG144

更新时间： 2024-01-24 04:19:46

品牌	Logo	应用领域
美高森美 - MICROSEMI		时钟栅可编程逻辑
页数	文件大小	规格书
178页	5602K
描述
Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 108MHz, 24576-Cell, CMOS, PBGA144, 13 X 13 MM, 1.45 MM HEIGHT, 1 MM PITCH, FBGA-144

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技术参数
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M1AGL1000V5-FFG144 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	LBGA, BGA144,12X12,40	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.88
最大时钟频率：	108 MHz	JESD-30 代码：	S-PBGA-B144
JESD-609代码：	e0	长度：	13 mm
湿度敏感等级：	3	可配置逻辑块数量：	24576
等效关口数量：	1000000	输入次数：	97
逻辑单元数量：	24576	输出次数：	97
端子数量：	144	最高工作温度：	70 °C
最低工作温度：		组织：	24576 CLBS, 1000000 GATES
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA144,12X12,40	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE	峰值回流温度（摄氏度）：	225
电源：	1.5 V	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	座面最大高度：	1.55 mm
子类别：	Field Programmable Gate Arrays	最大供电电压：	1.575 V
最小供电电压：	1.425 V	标称供电电压：	1.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD SILVER
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	13 mm	Base Number Matches：	1

M1AGL1000V5-FFG144 数据手册

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Product Brief

1 – IGLOO Low-Power Flash FPGAs

with Flash*Freeze Technology

Advanced I/O

Features and Benefits

• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage

Operation

Low Power

• 1.2 V or 1.5 V Core and I/O Voltage for Low Power

• Supports Single-Voltage System Operation

• 5 µW Power Consumption in Flash*Freeze Mode

• Low-Power Active FPGA Operation

• Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Easy Entry to / Exit from Ultra-Low-Power

Flash*Freeze Mode

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V

†

PCI-X , and LVCMOS 2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, BLVDS, and

M-LVDS (AGL250 and above)

• I/O Registers on Input, Output, and Enable Paths

‡

• Hot-Swappable and Cold-Sparing I/Os

High Capacity

†

• Programmable Output Slew Rate and Drive Strength

• 15 k to 1 Million System Gates

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO Family

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal, Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

Clock Conditioning Circuit (CCC) and PLL^†

• Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities, and External Feedback

• Retains Programmed Design When Powered Off

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

In-System Programming (ISP) and Security

Embedded Memory

• Secure ISP Using On-Chip 128-Bit Advanced

Encryption Standard (AES) Decryption (except ARM -

• 1 kbit of FlashROM User Nonvolatile Memory

†

enabled IGLOO

devices) via JTAG (IEEE 1532–

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit

†

compliant)

RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

†

to Secure FPGA Contents

H^•igh^Fla-P^she^Lr^of^co^krmance Routing Hierarchy

A^•RM^TruP^er^Do^uc^ae^l-s^Ps^oo^rtr^SS^RAu^Mpp^(eo^xr^ct^epi^tn^×I¹G⁸⁾LOO FPGAs

• M1 IGLOO Devices—Cortex™-M1 Soft Processor

Available with or without Debug

• Segmented, Hierarchical Routing and Clock Structure

Table 1-1 • IGLOO Product Family

IGLOO Devices

AGL015

AGL030

AGL060 AGL125 AGL250

AGL600

AGL1000

ARM-Enabled IGLOO Devices

System Gates

M1AGL250 M1AGL600 M1AGL1000

15 k

128

384

30 k

256

768

60 k

512

1,536

125 k

1,024

3,072

250 k

–

600 k

–

1 M

–

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

Flash*Freeze Mode (typical, µW)

RAM kbits (1,024 bits)

4,608-Bit Blocks

6,144

13,824

24,576

–

108

144

–

FlashROM Bits

1 k

–

1 k

–

1 k

Yes

1 k

Yes

1 k

Yes

1 k

Yes

1 k

Yes

Secure (AES) ISP

Integrated PLL in CCCs

–

VersaNet Globals

I/O Banks

Maximum User I/Os

133

143

235

300

Package Pins

3,5

UC81, CS81

QN132

VQ100

CS121

CS196

CS281

QFN

QN68

QN132

QN132 QN132

VQFP

FBGA

VQ100 VQ100

VQ100

FG144

FG144,

FG256,

FG484

FG144,

FG256,

FG484

Notes:

1. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.

2. For higher densities and support of additional features, refer to the IGLOOe Low-Power Flash FPGAs with

Flash*Freeze Technology handbook.

3. Device/package support TBD.

4. AES is not available for ARM-enabled IGLOO devices.

5. The M1AGL250 device does not support this package.

†

AGL015 and AGL030 devices do not support this feature.

‡

Supported only by AGL015 and AGL030 devices.

March 2008

Product Brief

1-1

12 3 4 5 6 7...178

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与M1AGL1000V5-FFG144相关器件

型号	品牌	获取价格	描述	数据表
M1AGL1000V5-FFG256	ACTEL	获取价格	Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 108MHz, 24576-Cell, CMOS, PBGA25
M1AGL1000V5-FFG484	ACTEL	获取价格	Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 108MHz, 24576-Cell, CMOS, PBGA48
M1AGL1000V5-FFGG144	ACTEL	获取价格	Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 108MHz, 24576-Cell, CMOS, PBGA14
M1AGL1000V5-FG144	MICROSEMI	获取价格	Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 108MHz, CMOS, PBGA144, 13 X 13 M
M1AGL1000V5-FG144YC	MICROSEMI	获取价格	Field Programmable Gate Array
M1AGL1000V5-FG256	MICROSEMI	获取价格	Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 108MHz, CMOS, PBGA256, 17 X 17 M
M1AGL1000V5-FG256I	MICROSEMI	获取价格	Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 108MHz, CMOS, PBGA256, 17 X 17 M
M1AGL1000V5-FG484	MICROSEMI	获取价格	Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 108MHz, CMOS, PBGA484, 23 X 23 M
M1AGL1000V5-FG484I	MICROSEMI	获取价格	Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 108MHz, CMOS, PBGA484, 23 X 23 M
M1AGL1000V5-FGG144I	MICROSEMI	获取价格	Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 108MHz, CMOS, PBGA144, 13 X 13 M

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