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M1020-12-167.3280LF PDF预览

M1020-12-167.3280LF

更新时间： 2024-01-28 15:02:41
品牌 Logo 应用领域
艾迪悌 - IDT ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
10页 440K
描述
Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36

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M1020-12-167.3280LF 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：LCC
包装说明：QCCN,针数：36
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.8JESD-30 代码：S-CQCC-N36
JESD-609代码：e3长度：8.99 mm
功能数量：1端子数量：36
最高工作温度：70 °C最低工作温度：
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：3.1 mm标称供电电压：3.3 V
表面贴装：YES电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：COMMERCIAL端子面层：MATTE TIN
端子形式：NO LEAD端子节距：0.635 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：8.99 mmBase Number Matches：1

M1020-12-167.3280LF 数据手册

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M1020/21  
Integrated  
Circuit  
Systems, Inc.  
VCSO BASED  
CLOCK PLL  
P r o d u c t D a t a S h e e t  
PIN DESCRIPTIONS  
Number  
1, 2, 3, 10, 14, 26  
Name  
GND  
I/O  
Ground  
Configuration  
Description  
Power supply ground connections.  
4
9
OP_IN  
nOP_IN  
Input  
External loop filter connections.  
See Figure 5, External Loop Filter, on pg. 6.  
5
8
nOP_OUT  
OP_OUT  
Output  
6
7
nVC  
VC  
Input  
11, 19, 33  
VCC  
Power  
Power supply connection, connect to +3.3V.  
FOUT1  
nFOUT1  
12  
13  
Output No internal terminator  
Output No internal terminator  
Internal pull-down resistor  
Clock output 1. Differential LVPECL (CML, LVDS available).  
FOUT0  
nFOUT0  
15  
16  
Clock output 0. Differential LVPECL (CML, LVDS available).  
17  
18  
P_SEL1  
P_SEL0  
Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 5,  
P Divider Look-Up Table (LUT), on pg. 4.  
1
2
20  
21  
nDIF_REF1  
DIF_REF1  
Biased to Vcc/2  
Reference clock input pair 1. Differential LVPECL or LVDS.  
Resistor bias on inverting terminal supports TTL or LVCMOS.  
Input  
1
1
Internal pull-down resistor  
Reference clock input selection. LVCMOS/LVTTL:  
Logic 1 selects DIF_REF1, nDIF_REF1.  
Logic 0 selects DIF_REF0, nDIF_REF0.  
22  
REF_SEL  
Input  
Input  
Internal pull-down resistor  
2
23  
24  
nDIF_REF0  
DIF_REF0  
Biased to Vcc/2  
Reference clock input pair 0. Differential LVPECL or LVDS.  
Resistor bias on inverting terminal supports TTL or LVCMOS.  
1
Internal pull-down resistor  
25  
27  
28  
29  
30  
NC  
No internal connection.  
MR_SEL3  
MR_SEL2  
MR_SEL0  
MR_SEL1  
M and R divider value selection. LVCMOS/ LVTTL.  
Internal pull-down resistor See Tables 3 and 4, M and R Divider Look-Up Tables (LUT)  
on pg. 3.  
1
Input  
Loss of Lock indicator output. Asserted when internal PLL is  
3
not tracking the input reference for frequency and phase.  
Logic 1 indicates loss of lock.  
31  
LOL  
Output  
Input  
Logic 0 indicates locked condition.  
Narrow Bandwidth enable. LVCMOS/LVTTL:  
Logic 1 - Narrow loop bandwidth, RIN = 2100kΩ.  
1
32  
NBW  
DNC  
Internal pull-UP resistor  
Logic 0 - Wide bandwidth, RIN = 100kΩ.  
Internal nodes. Connection to these pins can cause erratic  
34, 35, 36  
Do Not Connect.  
device operation.  
Table 2: Pin Descriptions  
Note 1: For typical values of internal pull-down and pull-UP resistors, see DC Characteristics on pg. 8.  
Note 2: Biased toVcc/2, with 50kΩ to Vcc and 50kΩ to ground. See Differential Inputs Biased to VCC/2 on pg. 8.  
Note 3: See LVCMOS Output in DC Characteristics on pg. 8.  
M1020/21 Datasheet Rev 1.0  
2 of 10  
Revised 28Jul2004  
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400  
1234567...10

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