®
LY24C02/04/08/16
2K/4K/8K/16K-bit 2-Wire Serial EEPROM
Preliminary. 0.4
AC ELECTRICAL CHARACTERISTICS
PARAMETER
SYM.
UNIT
Conditions Vcc = 1.8 to 5.5V Vcc = 2.5 to 5.5V
(Standard Mode) (Fast Mode)
MIN.
MAX.
MIN.
MAX.
External clock frequency
Clock high time
Clock low time
Rising time
Falling time
Start condition hold time
Start condition setup time
Data input hold time
Data input setup time
Stop condition setup time
fCLK
tHIGH
tLOW
tR
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
-
-
-
0
4
4.7
-
-
4
4.7
0
0.25
4
100
-
-
1
0.3
-
-
-
-
-
0
0.6
1.3
-
400
-
-
0.3
0.3
-
-
-
-
-
kHz
us
us
us
us
us
us
us
us
us
us
SDA, SCL
SDA, SCL
-
-
-
-
-
0.6
0.6
0
0.1
0.6
-
Before new
transmission
Bus free time
tBUF
4.7
-
1.3
-
Data output valid from clock low(note) tAA
-
-
-
0.3
-
-
3.5
100
5
-
-
-
0.9
50
5
us
ns
ms
Noise spike width
Write cycle time
Notes:
tSP
tWR
1. Upon customers request up to 400 kHz (Max.)in standard mode and 1 MHz in fast mode are available.
2. When acting as a transmitter, the LY24C02/04/08/16 must provide an internal minimum delay time to bridge the undefined (minimum 300
ns)
Of the falling edge of SCL. This is required to avoid unintended generation of a start or stop condition.
FUNCTION DESCRIPTION
I2C-BUS INTERFACE
The LY24C02/04/08/16 supports the I2C-bus serial interface data transmission protocol.
The 2-wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines
must be connected to VCC by a pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the
bus is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop
conditions, controlling bus access. The A2, A1 and A0 pins are device address inputs that are hard wired for
the LY24C02/04/08/16. As many as eight for 2K (four for 4K,two for 8K, one for 16K )devices may be
addressed on a single bus system.
A0, A1, A2
The A0, A1 and A2 pins are device address inputs that are hard wired for the LY24C02. As many as eight for
2K devices may be addressed on a single bus system.
The LY24C04 uses A1 and A2 pins for hard wire addressing and a total of four 4K devices may be addressed
on a single bus system. The A0 pin is not connected in the LY24C04.
The LY24C08 only use the A2 input for hard wire addressing and a total of two 8K devices may be addressed
on a single bus system. The A0 and A1 pins are no connects in the LY24C08.
The LY24C16 does not use the A0, A1, A2 device address pins. so the A0, A1, A2 pins have no connection.
I2C-BUS PROTOCOLS
Here are several rules for I2C-bus transfers:
— A new data transfer can be initiated only when the bus is currently not busy.
— MSB is always transferred first in transmitting data.
— During a data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
40 Hsuch-Fu Rd., Hsinchu, Taiwan.
TEL: 886-3-5165511
FAX: 886-3-5165522
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