LTC3809
PIN FUNCTIONS
PLLLPF(Pin1):FrequencySet/PLLLowpassFilter. When
synchronizing to an external clock, this pin serves as the
lowpass filter point for the phase-locked loop. Normally,
a series RC is connected between this pin and ground.
RUN (Pin 5): Run Control Input. Forcing this pin below
1.1V shuts down the chip. Driving this pin to V or releas-
IN
ing this pin enables the chip to start-up with the internal
soft-start.
When not synchronizing to an ex ternal clock, this pin ser ves
asthefrequencyselectinput. TyingthispintoGNDselects
IPRG (Pin 6): Three-State Pin to Select Maximum Peak
Sense Voltage Threshold. This pin selects the maximum
300kHz operation; tying this pin to V selects 750kHz
allowed voltage drop between the V and SW pins (i.e.,
IN
IN
operation. Floating this pin selects 550kHz operation.
the maximum allowed drop across the external P-channel
MOSFET). Tie to V , GND or float to select 204mV, 85mV
IN
Connect a 2.2nF capacitor between this pin and GND, and
a 1000pF capacitor between this pin and the SYNC/MODE
when using spread spectrum modulation operation.
or 125mV respectively.
BG (Pin 7): Bottom (NMOS) Gate Drive Output. This pin
drives the gate of the external N-channel MOSFET. This
SYNC/MODE (Pin 2): This pin performs four functions:
1) auxiliary winding feedback input, 2) external clock
synchronization input for phase-locked loop, 3) Burst
Mode, pulse-skipping or forced continuous mode select,
and 4) enable spread spectrum modulation operation in
pulse-skipping mode. Applying a clock with frequency
between 250kHz to 750kHz causes the internal oscillator
to phase-lock to the external clock and disables Burst
Mode operation but allows pulse-skipping at low load
currents.
pin has an output swing from PGND to V .
IN
TG (Pin 8): Top (PMOS) Gate Drive Output. This pin drives
the gate of the external P-channel MOSFET. This pin has
an output swing from PGND to V .
IN
V
(Pin 9): Chip Signal Power Supply. This pin powers
IN
the entire chip, the gate drivers and serves as the positive
input to the differential current comparator.
SW (Pin 10): Switch Node Connection to Inductor. This
pin is also the negative input to the differential current
comparatorandaninputtothereversecurrentcomparator.
Normally this pin is connected to the drain of the external
P-channel MOSFET, the drain of the external N-channel
MOSFET and the inductor.
To select Burst Mode operation at light loads, tie this
pin to V . Grounding this pin selects forced continuous
IN
operation, which allows the inductor current to reverse.
TyingthispintoV selectspulse-skippingmode. Inthese
FB
cases, the frequency of the internal oscillator is set by the
GND (Pin 11): Exposed Pad. The Exposed Pad is ground
and must be soldered to the PCB ground for electrical
contact and optimum thermal performance.
voltage on the PLLLPF pin. Tying to a voltage between
1.35V to V – 0.5V enables spread spectrum modulation
IN
operation. In this case, an internal 2.6μA pull-down current
sourcehelpstosetthevoltageatthispinbytyingaresistor
with appropriate value between this pin and V . Do not
IN
leave this pin floating.
V
(Pin 3): Feedback Pin. This pin receives the remotely
FB
sensedfeedbackvoltageforthecontrollerfromanexternal
resistor divider across the output.
ITH (Pin 4): Current Threshold and Error Amplifier
Compensation Point. Nominal operating range on this pin
is from 0.7V to 2V. The voltage on this pin determines the
threshold of the main current comparator.
3809fc
6
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