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LTC2953IDD-1-TRPBF PDF预览

LTC2953IDD-1-TRPBF

更新时间： 2024-02-28 22:30:17
品牌 Logo 应用领域
凌特 - Linear 监控控制器
页数 文件大小 规格书
20页 199K
描述
Push Button On/Off Controller with Voltage Monitoring

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LTC2953IDD-1-TRPBF 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active包装说明：HVSON,
针数：12Reach Compliance Code：compliant
风险等级：5.14可调阈值：YES
模拟集成电路 - 其他类型：POWER SUPPLY SUPPORT CIRCUITJESD-30 代码：S-PDSO-N12
JESD-609代码：e3长度：3 mm
湿度敏感等级：1信道数量：1
功能数量：1端子数量：12
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HVSON
封装形状：SQUARE封装形式：SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：0.8 mm最大供电电压 (Vsup)：27 V
最小供电电压 (Vsup)：2.7 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.45 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：3 mmBase Number Matches：1

LTC2953IDD-1-TRPBF 数据手册

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LTC2953  
PIN FUNCTIONS  
GND (Pin 1): Ground.  
⎯
⎯
⎯
of hysteresis. PFI controls the state of the PFO output pin  
⎯
⎯
and is independent of PB, Vꢁ and UVLO status. Connect  
to GND if unused.  
VM (Pin 2): Voltage ꢁonitor Input. Input to an accurate  
comparator with a 0.5V threshold. Vꢁ controls the state  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯ ⎯ ⎯  
PFO (Pin 9): Power Fail Output. This pin is a high voltage  
open drain pull-down. PFO pulls low when PFI is below  
0.5V. Open circuit when unused.  
of the RST output pin and is independent of PB, PFI and  
UVLO status. A voltage below 0.5V on this pin asserts  
⎯
⎯
⎯
⎯
⎯
⎯
RST low. Connect to GND if unused.  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
KILL (Pin 3): KILL Input. Forcing KILL low releases the  
RST (Pin 10): Reset Output. This pin is an open drain  
pull-down. Pulls low when Vꢁ input is below 0.5V and is  
held low for 200ms after Vꢁ input is above 0.5V. Open  
circuit when unused.  
enable output. During system turn on, this pin is blanked  
by a 512ms internal timer (t  
system to pull KILL high. This pin has an accurate 0.6V  
threshold and can be used as a power kill voltage monitor.  
Set the pin voltage above its threshold if unused.  
) to allow the  
KILL, ON BLANK  
⎯
⎯
⎯
⎯
EN (LTC2953-1, Pin 11): Open Drain Enable Output. This  
output is intended to enable system power. EN is asserted  
⎯
⎯
PDT (Pin 4): Power Down Time Input. A capacitor to  
high after a valid PB turn on event (t  
). EN is released  
DB, ON  
⎯
⎯
⎯
⎯
ground determines the additional time (6.4 seconds/μF)  
low if: a) KILL is not driven high (by μP) within 512ms of  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
that PB or UVLO must be held low before releasing the  
the initial valid PB power turn on event, b) KILL is driven  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
EN/EN and INT outputs. If this pin is left open, the power  
down delay time defaults to 64ms.  
lowduringnormaloperation,c)PBorUVLOisassertedand  
held low (t > t + t ) during normal operation.  
PD, ꢁin  
PDT  
⎯
⎯
⎯
⎯
⎯ ⎯  
EN (LTC2953-2, Pin 11): Open Drain Enable Output. This  
PB (Pin 5): Push Button Input. Connecting PB to ground  
⎯ ⎯  
output is intended to enable system power. EN is asserted  
throughamomentaryswitchprovidesOn/Offcontrolviathe  
EN/EN and INT outputs. An internal 100k pull-up resistor  
connects to an internal 1.9V bias voltage. The rugged PB  
input withstands 10kV ESD HBꢁ and can be pulled up to  
27V externally without consuming extra current. Voltages  
below ground will not damage the pin.  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
low after a valid PB turn on event (t  
). EN is released  
DB, ON  
⎯
⎯
⎯
⎯
⎯
⎯
high if: a) KILL is not driven high (by μP) within 512ms of  
the initial valid PB power turn-on event, b) KILL is driven  
lowduringnormaloperation,c)PBorUVLOisassertedand  
held low (t > t + t ) during normal operation.  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PD, ꢁin  
PDT  
⎯
⎯
⎯
V (Pin 6): Power Supply Input: 2.7V to 27V.  
INT (Pin 12): Open Drain Interrupt Output. After a turn off  
IN  
⎯ ⎯  
) from PB or UVLO, the LTC2953  
event is detected (t  
DB, OFF  
UVLO(Pin7):UVLOComparatorInput.WhenUVLOdrops  
⎯
⎯
⎯
interrupts the system (μP) by asserting INT low. The μP  
would perform power down and housekeeping tasks and  
below its falling threshold (0.5V) for more than 32ms, the  
⎯
⎯
⎯
LTC2953 asserts INT low, thereby requesting a system  
power down. If UVLO remains below its falling threshold  
(0.5V) for longer than the adjustable power down delay,  
the enable output is released. Additionally, UVLO provides  
⎯
⎯
⎯
⎯
thenasserttheKILLpinlow, thusreleasingtheenableout-  
⎯
⎯
⎯
put. The INT pulse width is a minimum of 32ms and stays  
⎯
⎯
⎯
⎯
low as long as PB is asserted. If PB is asserted for longer  
⎯ ⎯ ⎯  
+ t , however, the INT and EN/EN outputs  
PDT  
⎯
⎯
than t  
PD, ꢁin  
⎯
⎯
a PB lock out feature that prevents the user from asserting  
the enable output when UVLO falls below its threshold.  
are immediately released. Open circuit when unused.  
Connect to V if unused.  
Exposed Pad (Pin 13): Exposed Pad may be left open or  
connected to ground.  
IN  
PFI (Pin 8): Power Fail Comparator Input. Input to an ac-  
curate comparator with a 0.5V falling threshold and 4mV  
2953f  
7
1...45678910...20

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