LTC1669CMS8#TR

更新时间： 2024-02-17 02:32:10

品牌	Logo	应用领域
凌特 - Linear		转换器光电二极管
页数	文件大小	规格书
12页	186K
描述
暂无描述

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

LTC1669CMS8#TR 数据手册

LTC1669

PIN FUNCTIONS

SDA (Pin 1, Pin 1 on SOT-23): Serial Data Bidirectional

Pin. Data is shifted into the SDA pin and acknowledged by

the SDA pin. High impedance pin while data is shifted in.

Open-drain N-channel output during acknowledgment.

Requires a pull-up resistor or current source to V_CC.

V_CC(Pin 5, Pin 4 on SOT-23): Power Supply. 2.7V ≤ V_CC

≤ 5.5V. Also used as the reference voltage input when the

part is programmed to use V_CCas the reference.

AD0 (Pin 6): Slave Address Select Bit 0. Tie this pin to

either V_CCor GND to modify the corresponding bit of the

LTC1669’s slave address.

AD1 (Pin 2): Slave Address Select Bit 1. Tie this pin to

either V_CCor GND to modify the corresponding bit of the

LTC1669’s slave address.

GND (Pin 7, Pin 2 on SOT-23): System Ground.

_OUT(Pin 8, Pin 3 on SOT-23): Voltage Output. Buffered

AD2 (Pin 3): Slave Address Select Bit 2. Tie this pin to

either V_CCor GND to modify the corresponding bit of the

LTC1669’s slave address.

rail-to-rail DAC output.

SCL (Pin 4, Pin 5 on SOT-23): Serial Clock Input Pin. Data

is shifted into the SDA pin at the rising edges of the clock.

This high impedance pin requires a pull-up resistor or

current source to V_CC.

DEFINITIONS

Differential Nonlinearity (DNL): The difference between

the measured change and the ideal 1LSB change for any

twoadjacentcodes.TheDNLerrorbetweenanytwocodes

is calculated as follows:

zero. The INL error at a given input code is calculated as

follows:

INL = [V_OUT– V_OS– (V_FS– V_OS)(code/1023)]/LSB

Where V_OUTis the output voltage of the DAC measured at

the given input code.

DNL = (∆V_OUT– LSB)/LSB

Where ∆V_OUTis the measured voltage difference between

two adjacent codes.

Least Significant Bit (LSB): The ideal voltage difference

between two successive codes.

DigitalFeedthrough: Theglitchthatappearsattheanalog

outputcausedbyACcouplingfromthedigitalinputswhen

they change state. The area of the glitch is specified in

(nV)(sec).

LSB = V_REF/1024

Resolution (n): Defines the number of DAC output states

(2ⁿ) that divide the full-scale range. Resolution does not

imply linearity.

Full-Scale Error (FSE): The deviation of the actual full-

scale voltage from ideal. FSE includes the effects of offset

and gain errors (see Applications Information).

Voltage Offset Error (V_OS): Nominally, the voltage at the

output when the DAC is loaded with all zeros. A single

supply DAC can have a true negative offset, but the output

cannot go below zero (see Applications Information).

Integral Nonlinearity (INL): The deviation from a straight

line passing through the endpoints of the DAC transfer

curve(EndpointINL).Becausetheoutputcannotgobelow

zero, the linearity is measured between full scale and the

lowestcodethatguaranteestheoutputwillbegreaterthan

For this reason, single supply DAC offset is measured at

the lowest code that guarantees the output will be greater

than zero.

1669f

1 2 3 456 7 8...12

下载PDF

与LTC1669CMS8#TR相关器件

型号	品牌	描述	获取价格	数据表
LTC1669CMS8#TRPBF	Linear	LTC1669 - 10-Bit Rail-to-Rail Micropower DAC with I<sup>2</sup>C Interface; Pa	获取价格
LTC1669CS5	Linear	10-Bit Rail-to-Rail Micropower DAC with I2C Interface	获取价格
LTC1669CS5#TRPBF	Linear	LTC1669 - 10-Bit Rail-to-Rail Micropower DAC with I<sup>2</sup>C Interface; Pa	获取价格
LTC1669IMS8	Linear	10-Bit Rail-to-Rail Micropower DAC with I2C Interface	获取价格
LTC1669IMS8#PBF	Linear	LTC1669 - 10-Bit Rail-to-Rail Micropower DAC with I<sup>2</sup>C Interface; Pa	获取价格
LTC1669IMS8#TR	Linear	LTC1669 - 10-Bit Rail-to-Rail Micropower DAC with I<sup>2</sup>C Interface; Pa	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

LTC1669CMS8#TR

LTC1669CMS8#TR 数据手册

与LTC1669CMS8#TR相关器件

与LTC1669CMS8#TR相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

LTC1669CMS8#TR

LTC1669CMS8#TR 数据手册

与LTC1669CMS8#TR相关器件

与LTC1669CMS8#TR相关文章

您还可以找

您在本页遇到什么问题？