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LTC1669CMS8#TR PDF预览

LTC1669CMS8#TR

更新时间: 2024-02-01 12:36:45
品牌 Logo 应用领域
凌特 - Linear 转换器光电二极管
页数 文件大小 规格书
12页 186K
描述
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LTC1669CMS8#TR 数据手册

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LTC1669  
U
W U U  
APPLICATIONS INFORMATION  
Slave Address (SOT-23 Package)  
The Bandgap (BG) bit when set to “0” selects the DAC  
supply voltage as its voltage reference. The full-scale  
output of the DAC with this setting is equal to the supply  
voltage. When the BG bit is set to “1,” the internal bandgap  
reference(1.25V)isselectedastheDAC’sreference. The  
full-scale output voltage for this setting is 2.5V.  
The slave address for the SOT-23 package has been  
factory programmed to be “0100 000” (LTC1669) and  
“0100 001” (LTC1669-1). If another address is required,  
please consult the factory.  
Command Byte  
Data Bytes  
7
6
5
4
3
2
1
0
Least Significant Data Byte  
X
X
X
X
X
BG  
SD  
SY  
7
6
5
4
3
2
1
0
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
SY  
1
0
Allows update on Acknowledge of SYNC Address only  
Update on Stop condition only (Power-On Default)  
Most Significant Data Byte  
SD  
1
0
Puts the device in power-down mode  
Puts the device in standard operating mode  
(Power-On Default)  
7
6
5
4
3
2
1
0
X
X
X
X
X
X
D9  
D8  
X = Don’t care  
BG  
X
1
0
Selects the internal bandgap reference  
Selects the supply as the reference (Power-On Default)  
Send Byte Protocol  
X
Don’t Care  
The Send Byte protocol used on the LTC1669 is actually a  
subset of the Write Word protocol described previously.  
The Send Byte protocol can only be used to send the  
command byte information to the LTC1669.  
The stop condition normally initiates the update of the  
DAC’s output latches. Simultaneous update of more than  
one DAC or other devices on the bus can be achieved by  
reissuing new start bit, address, command and data bytes  
before issuing a final stop condition (which will update all  
the devices). An alternate way to achieve simultaneous  
LTC1669 updates is to override the stop condition update  
by setting the “SY” bit of the command byte. Setting this  
bit sets the device to update the DAC output latches only  
at the reception of a SYNC address quick command. The  
actual update occurs on the rising edge of SCL during the  
Acknowledge. In this way, all devices can update on the  
reception of the SYNC address quick command instead of  
the STOP condition.  
1
7
1
1
8
1
1
S
Slave Address Wr  
A
Command Byte  
A
P
S = Start Condition, Wr = Write Bit, A = Acknowledge, P = Stop Condition  
1669 TA04  
The Send Byte protocol is also used whenever the Write  
Word protocol is interrupted for any reason. Reception of  
a START or STOP condition after the Acknowledge of the  
command byte, but before the Acknowledge of the last  
data byte, will cause both data bytes to be ignored and the  
command byte to be accepted.  
Reception of a START or STOP condition before the  
Acknowledge of the command byte will cause the inter-  
rupted command byte to be ignored.  
A Shutdown (SD) bit = HIGH will put the device in a low  
powerstatebutretainalldatalatchinformation.Shutdown  
will occur at the reception of a STOP condition. This way  
shutdown could be synchronized to other devices. The  
output impedance of the DAC will go to a high impedance  
state (500kto GND).  
1669f  
8

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