LTC1164-6
U
U
U
(14-Lead Dual-In-Line Package)
PI FU CTIO S
could go above ground, a signal diode must be used to
clampV.Figures1and2showtypicalconnectionsfordual
and single supply operation.
buffer,Figure3,canbeusedprovidedthatitsinputcommon
mode range is well within the filter’s output swing. Pin 6 is
an intermediate filter output providing an unspecified 6th
order lowpass filter. Pin 6 should not be loaded.
–
V
1
2
3
4
5
6
7
14
13
12
11
10
9
*
ELLIPTIC/LINEARPHASE(Pin10):TheDClevelatthispin
selects the desired filter response, elliptic or linear phase
and determines the ratio of the clock frequency to the
cutoff frequency of the filter. Pin 10 connected to V–
provides an elliptic lowpass filter with clock-to-fCUTOFF
ratio of 100:1. Pin 10 connected to analog ground pro-
vides a linear phase lowpass filter with a clock- to-f–3dB
ratio of 160:1 and a transient response overshoot of 1%.
When Pin 10 is connected to V+ the clock-to-fCUTOFF ratio
is 50:1 and the filter response is elliptic. Bypassing Pin 10
to analog ground reduces the output DC offsets. If the DC
level at Pin 10 is switched mechanically or electrically at
slewratesgreaterthan1V/µswhilethedeviceisoperating,
a10kresistorshouldbeconnectedbetweenPin10andthe
DC source.
V
V
0.1µF
IN
+
1k
CLOCK SOURCE
LTC1164-6
0.1µF
GND
DIGITAL SUPPLY
+
8
* OPTIONAL
V
1164-6 F01
OUT
Figure 1. Dual Supply Operation for f /f
= 100:1
CLK CUTOFF
1
2
3
4
5
6
7
14
13
12
11
10
9
V
IN
+
1k
V
LTC1164-6
CLOCK SOURCE
0.1µF
CLK (Pin 11): Any TTL or CMOS clock source with a
square-wave output and 50% duty cycle (±10%) is an
adequateclocksourceforthedevice.Thepowersupplyfor
the clock source should not be the filter’s power supply.
The analog ground for the filter should be connected to
clock’s ground at a single point only. Table 1 shows the
clock’s low and high level threshold value for a dual or
single supply operation. A pulse generator can be used as
a clock source provided the high level ON time is greater
than 0.5µs. Sine waves are not recommended for clock
input frequencies less than 100kHz, since excessively
slow clock rise or fall times generate internal clock jitter
(maximum clock rise or fall time ≤ 1µs). The clock signal
should be routed from the right side of the IC package to
avoid coupling into any input or output analog signal path.
A 1k resistor between clock source and Pin 11 will slow
down the rise and fall times of the clock to further reduce
charge coupling, Figures 1 and 2.
GND
DIGITAL SUPPLY
10k
10k
+
8
+
1µF
V
OUT
1164-6 F02
Figure 2. Single Supply Operation for f /f
= 100:1
CLK CUTOFF
Table 1. Clock Source High and Low Threshold Levels
POWER SUPPLY
Dual Supply = ±7.5V
Dual Supply = ±5V
Dual Supply = ±2.5V
Single Supply = 12V
Single Supply = 5V
HIGH LEVEL
≥ 2.18V
≥ 1.45V
≥ 0.73V
≥ 7.80V
≥ 1.45V
LOW LEVEL
≤ 0.5V
≤ 0.5V
≤ – 2.0V
≤ 6.5V
≤ 0.5V
V– (Pins 7, 14): Pins 7 and 14 should be connected
together. In a printed circuit board the connection should
be done under the IC package through a short trace
surrounded by the analog ground plane.
–
VOUT (Pins 9, 6): Pin 9 is the specified output of the filter;
it can typically source or sink 1mA. Driving coaxial cables
or resistive loads less than 20k will degrade the total
harmonicdistortionofthefilter.Whenevaluatingthedevice’s
distortion an output buffer is required. A noninverting
1k
+
LT1006, f < 5kHz
C
LT1200, f > 5kHz
C
1164-6 F03
Figure 3. Buffer for Filter Output
11646fa
7
5秒后页面跳转
PCF8574资料解读：主要参数分析、引脚说明
AD637数据手册解读：主要特性、引脚及其功能解读、电气参数
ADUM1201资料手册解读：参数分析、引脚说明、应用分析
一文带你了解压敏电阻器在直流电路中的过压保护作用
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
