LTC1067IS#TR

更新时间： 2024-02-21 23:58:56

品牌	Logo	应用领域
凌特 - Linear		/
页数	文件大小	规格书
20页	480K
描述
LTC1067 - Rail-to-Rail, Very Low Noise Universal Dual Filter Building Block; Package: SO; Pins: 16; Temperature Range: -40°C to 85°C

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技术参数
数据手册

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LTC1067IS#TR 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	SOP,
针数：	16	Reach Compliance Code：	compliant
风险等级：	5.58	有源滤波器类型：	SWITCHED CAPACITOR FILTER
中心频率或截止频率最大范围：	20 kHz	中心频率或截止频率最小范围：	0.001 kHz
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e3
长度：	9.906 mm	湿度敏感等级：	1
功能数量：	2	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	极和零点：	2 AND 0
认证状态：	Not Qualified	响应：	UNIVERSAL
座面最大高度：	1.752 mm	最大供电电压 (Vsup)：	11 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	4.75 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
传递特性：	RESISTOR PROGRAMMABLE	宽度：	3.899 mm
Base Number Matches：	1

LTC1067IS#TR 数据手册

LTC1067/LTC1067-50

PIN FUNCTIONS

SA, SB (Pins 4, 13):Summing Inputs. The summing pins’

connection, along with the other resistor connections,

determine the circuit topology (mode) of each 2nd order

section. These pins should never be left floating.

plane with at least a 1µF capacitor. An on-chip resistive

voltage divider sets the bias at one-half of the supply.

CLK (Pin 16): Clock Input. Any CMOS logic clock source

with a square-wave output and a 50% duty cycle (±10%)

is an adequate clock source for the device. The power

supplyfortheclocksourceshouldnotbethefilter’spower

supply. The analog ground for the filter should be con-

nected to the clock’s ground at a single point only. Table

1showstheclock’slowandhighlevelthresholdvaluesfor

dual supply or single supply operation. Logic low level

signals must be greater than the negative supply voltage.

With a ±5V power supply, the clock levels may be either

±5V or 0V to 5V. Logic high level signals should be less

than the positive supply voltage. However, when the

positive supply voltage is either 3V or 3.3V, the clock

signal can be as high as 5.5V.

LPA, BPA, HPA/NA, HPB/NB, BPB, LPB (Pins 5, 6, 7, 10,

11, 12): Output Pins. Each 2nd order section of the

LTC1067 has three outputs which typically source 33mA

and sink 2mA. Driving coaxial cable, capacitive loads or

resistive loads less than 10k will degrade the total har-

monic distortion performance ofany filter design. Referto

OutputLoadingintheApplicationsInformationsectionfor

more details. When evaluating the distortion or noise

performance of a filter, the output should be buffered with

a wideband amplifier.

INV A, INV B (Pins 8, 9): Inverting Input. These pins are

the high impedance inverting inputs of internal op amps.

They are susceptible to stray capacitance coupling to low

impedance nodes such as signal outputs and power

supply lines. Resistors that are connected from a signal

outputto theinverting inputpin should be locatedas close

to the inverting input as possible.

Table 1. Clock Source High and Low Threshold Levels

POWER SUPPLY

±5V

HIGH LEVEL

≥ 2.2V

LOW LEVEL

≤ 0.50V

Single 5V

≥ 2.2V

≤ 0.50V

Single 3V, 3.3V

≥ 2V

≤ 0.40V

Sine waves are not recommended for the clock input. The

clock signal should be routed from the right side of the IC

package to avoid coupling to any power supply lines or

input or output signal paths. A 200Ω resistor between the

clock source and Pin 16 will slow down the rise and fall

times of the clock to reduce charge coupling of the clock.

This will result in less clock feedthrough noise on the

output signal.

AGND (Pin 15): Analog Ground. The filter performance

depends on the quality of the analog signal ground. For

either dual or single supply operation, an analog ground

plane surrounding the package is recommended. The

analog ground plane should be connected to any digital

ground at a single point. For dual supply operation Pin 15

is connected to the analog ground plane. For single supply

operationPin15shouldbebypassedtotheanalogground

BLOCK DIAGRA

HPA/NA

LPA

BPA

INV A

–

∑

–

15k

AGND

BPB

LPB

HPB/NB

–

∑

–

INV B

–

1067 BD

CLK

1...5 6 789 10 11...20

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与LTC1067IS#TR相关器件

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LTC1067IS#TRPBF	Linear	LTC1067 - Rail-to-Rail, Very Low Noise Universal Dual Filter Building Block; Package: SO;	获取价格
LTC1068	Linear	Clock-Tunable, Quad Second Order, Filter Building Blocks	获取价格
LTC1068	ADI	时钟可调、四通道二阶滤波器单元式部件	获取价格
LTC1068-200CG	Linear	Clock-Tunable, Quad Second Order, Filter Building Blocks	获取价格
LTC1068-200CG#PBF	Linear	LTC1068 - Clock-Tunable, Quad Second Order, Filter Building Blocks; Package: SSOP; Pins: 2	获取价格
LTC1068-200CG#TRPBF	Linear	LTC1068 - Clock-Tunable, Quad Second Order, Filter Building Blocks; Package: SSOP; Pins: 2	获取价格

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