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LTC1064_09

更新时间： 2022-12-28 23:35:34
品牌 Logo 应用领域
凌特 - Linear /
页数 文件大小 规格书
20页 262K
描述
Low Noise, Fast, Quad Universal Filter Building Block

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LTC1064_09 数据手册

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LTC1064  
ELECTRICAL CHARACTERISTICS  
(Complete Filter) The  
●
denotes the specifications which apply over the full  
operating temperature range, otherwise specifications are at V = ±5V, T = 25°C, TTL clock input level, unless otherwise specified.  
S
A
PARAMETER  
CONDITIONS  
V = ±8V, Q ≤ 3  
MIN  
TYP  
0.1 to 140  
0 to 1  
MAX  
UNITS  
kHz  
MHz  
Center Frequency Range, f  
Input Frequency Range  
O
S
Clock-to-Center Frequency  
Ratio, f /f  
LTC1064  
LTC1064A (Note 2)  
f
= 1MHz, f = 20kHz, Pin 17 High  
50 ± 0.3  
%
%
CLK  
O
Sides A, B, C: Mode 1,  
R1 = R3 = 5k, R2 = 5k, Q = 10,  
Sides D: Mode 3, R1 = R3 = 50k  
R2 = R4 = 5k  
●
●
50 ± 0.8  
50 ± 0.9  
CLK  
O
%
LTC1064  
LTC1064A (Note 2)  
Same as Above, Pin 17 Low, f  
= 1MHz  
100 ± 0.3  
%
%
CLK  
f = 10kHz  
O
Sides A, B, C  
Side D  
●
●
100 ± 0.8  
100 ± 0.9  
Clock-to-Center Frequency  
Ratio, Side-to-Side Matching LTC1064A (Note 2)  
LTC1064  
f
= 1MHz  
0.4  
%
%
CLK  
●
1
Clock-to-Center Frequency  
LTC1064  
LTC1064A (Note 2)  
f
= 4MHz, f = 80kHz, Pin 17 High  
50 ± 0.6  
%
%
CLK  
O
Ratio, f /f (Note 3)  
Sides A, B, C: Mode 1, V = ±7.5V  
50 ± 1.3  
CLK  
O
S
R1 = R3 = 50k, R2 = 5k, Q = 5  
Side D: Mode 3, R1 = R3 = 50k  
R2 = R4 = 5k, f  
= 4MHz  
CLK  
LTC1064  
LTC1064 A (Note 2)  
Same as Above, Pin 17 Low  
= 4MHz, f = 40kHz  
100 ± 0.6  
%
%
f
100 ± 1.3  
CLK  
O
Q Accuracy  
Sides A, B, C: Mode 1, Q = 10  
Side D: Mode 3, f = 1MHz  
●
●
±2  
±3  
6
8
%
%
CLK  
f Temperature Coefficient  
O
Mode 1, 50:1, f  
< 2MHz  
±1  
ppm/°C  
CLK  
Q Temperature Coefficient  
Mode 1, 100:1, f  
< 2MHz  
±5  
±5  
ppm/°C  
ppm/°C  
CLK  
Mode 3, f  
< 2MHz  
CLK  
DC Offset Voltage  
V
V
V
(Table 1)  
(Table 1)  
(Table 1)  
f
f
f
f
= 1MHz, 50:1 or 100:1  
= 1MHz, 50:1 or 100:1  
= 1MHz, 50:1 or 100:1  
< 1MHz  
●
●
●
2
3
3
0.2  
7
12  
15  
45  
45  
mV  
mV  
mV  
OS1  
OS2  
OS3  
CLK  
CLK  
CLK  
CLK  
Clock Feedthrough  
Maximum Clock Frequency  
Power Supply Current  
mV  
RMS  
MHz  
Mode 1, Q < 5, V ≥ ±5V  
S
9
23  
26  
mA  
mA  
●
Note 1: Absolute Maximum Ratings are those values beyond which the life  
of a device may be impaired.  
Note 2: Contact LTC Marketing.  
Note 3: Not tested, guaranteed by design.  
Table 1. Output DC Offsets, One 2nd Order Section  
V
V
V
OSLP  
PINS 4, 9, 16, 21  
OSN  
OSBP  
MODE  
PINS 2, 11, 14, 23  
PINS 3, 10, 15, 22  
1
1b  
2
V
V
V
[(1/Q) + 1 + ⏐⏐ ⏐⏐ ] – V /Q  
H
V
V
V
V
OSN  
– V  
OS1  
OS1  
OS1  
OLP  
OS3  
OS3  
OS3  
OS3  
OS2  
[(1/Q) + 1 + (R2/R1)] – V /Q  
~(V  
– V )[1 + (R5/R6)]  
OSN OS2  
OS3  
[(1 + (R2/R1) + (R2/R3) + (R2/R4) – V (R2/R3)]  
V
– V  
OSN OS2  
OS3  
× [R4/(R2 + R4)] + V [R2/(R2 + R4)]  
OS2  
3
V
V
V
[1 + (R4/R1) + (R4/R2) + (R4/R3)]  
OS1  
OS2  
OS3  
– V (R4/R2) – V (R4/R3)  
OS2  
OS3  
1064fb  
3
1234567...20

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