LT6555IUF

更新时间： 2024-01-06 04:11:13

品牌	Logo	应用领域
凌特 - Linear		复用器
页数	文件大小	规格书
16页	361K
描述
650MHz Gain of 2 Triple 2:1Video Multiplexer

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技术参数
数据手册

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LT6555IUF 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	VQCCN,
针数：	24	Reach Compliance Code：	compliant
风险等级：	5.3	模拟集成电路 - 其他类型：	VIDEO MULTIPLEXER
JESD-30 代码：	S-PQCC-N24	JESD-609代码：	e3
长度：	4 mm	湿度敏感等级：	1
负电源电压最大值（Vsup）：	-6 V	负电源电压最小值（Vsup）：	-2.25 V
标称负供电电压 (Vsup)：	-5 V	信道数量：	1
功能数量：	3	端子数量：	24
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	VQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	0.75 mm	最大供电电压 (Vsup)：	6 V
最小供电电压 (Vsup)：	2.25 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	BIPOLAR
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	4 mm	Base Number Matches：	1

LT6555IUF 数据手册

LT6555

PI FU CTIO S ^{(GN24 Package)}

IN1A (Pin 1): Channel 1 Input A. This pin has a nominal

impedance of 400kΩ and does not have any internal

termination resistor.

V^–(Pin15):NegativeSupplyVoltageforChannel3Output

Stage. V^–pins are not internally connected to each other

andmustallbeconnectedexternally.Propersupplybypass-

ingisnecessaryforbestperformance.SeetheApplications

Information section.

DGND (Pin 2): Digital Ground Reference for Enable Pin.

This pin is normally connected to ground.

OUT3 (Pin 16): Channel 3 Output. It is twice the selected

channel 3 input and performs optimally with a 150Ω load

(a double terminated 75Ω cable).

V⁺(Pin 17): Positive Supply Voltage for Channels 2 and 3

OutputStages.V⁺pinsarenotinternallyconnectedtoeach

other and must all be connected externally. Proper supply

bypassing is necessary for best performance. See the

Applications Information section.

IN2A (Pin 3): Channel 2 Input A. This pin has a nominal

impedance of 400kΩ and does not have any internal

termination resistor.

_REF(Pin 4): Voltage Reference for Input Clamping. This

is the tap to an internal voltage divider that defines mid-

supply. It is normally connected to ground in dual supply,

DC coupled applications.

IN3A (Pin 5): Channel 3 Input A. This pin has a nominal

impedance of 400kΩ and does not have any internal

termination resistor.

OUT2 (Pin 18): Channel 2 Output. It is twice the selected

channel 2 input and performs optimally with a 150Ω load

(a double terminated 75Ω cable).

V^–(Pin 19): Negative Supply Voltage for Channels 1 and

2OutputStages.V^–pinsarenotinternallyconnectedtoeach

other and must all be connected externally. Proper supply

bypassing is necessary for best performance. See the Ap-

plications Information section.

AGND1 (Pin 6): Analog Ground for the 360Ω Gain Resis-

tor of Channel 1.

IN1B (Pin 7): Channel 1 Input B. This pin has a nominal

impedance of 400kΩ and does not have any internal

termination resistor.

AGND2 (Pin 8): Analog Ground for the 360Ω Gain Resis-

OUT1 (Pin 20): Channel 1 Output. It is twice the selected

channel 1 input and performs optimally with a 150Ω load

(a double terminated 75Ω cable).

V⁺(Pin 21): Positive Supply Voltage for Channel 1 Output

Stage. V⁺pins are not internally connected to each other

and must all be connected externally. Proper supply

bypassing is necessary for best performance. See the

Applications Information section.

tor of Channel 2.

IN2B (Pin 9): Channel 2 Input B. This pin has a nominal

impedance of 400kΩ and does not have any internal

termination resistor.

AGND3 (Pin 10): Analog Ground for the 360Ω Gain

Resistor of Channel 3.

IN3B (Pin 11): Channel 3 Input B. This pin has a nominal

impedance of 400kΩ and does not have any internal

termination resistor.

V^–(Pin 12): Negative Supply Voltage. V^–pins are not in-

ternallyconnectedtoeachotherandmustallbeconnected

externally. Proper supply bypassing is necessary for best

performance. See the Applications Information section.

V⁺(Pins 13, 14, 24): Positive Supply Voltage. V⁺pins are

not internally connected to each other and must all be

connected externally. Proper supply bypassing is neces-

sary for best performance. See the Applications Informa-

tion section.

SEL (Pin 22): Select Pin. This high impedance pin selects

which set of inputs are sent to the output pins. When the

pin is pulled low, the A inputs are selected. When the pin

is pulled high, the B inputs are selected.

EN (Pin 23): Enable Control Pin. An internal pull-up

resistor of 46k defines the pin’s impedance and will turn

thepartoffifthepinisunconnected.Whenthepinispulled

low, the amplifiers are enabled.

Exposed Pad (Pin 25, QFN Only): The Exposed Pad is V^–

and must be soldered to the PCB. It is internally connected

to the QFN Pin 4, V^–.

6555f

1...4 5 678 9 10...16

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