LT6555IUF

更新时间： 2024-02-15 08:52:52

品牌	Logo	应用领域
凌特 - Linear		复用器
页数	文件大小	规格书
16页	361K
描述
650MHz Gain of 2 Triple 2:1Video Multiplexer

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技术参数
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LT6555IUF 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	VQCCN,
针数：	24	Reach Compliance Code：	compliant
风险等级：	5.3	模拟集成电路 - 其他类型：	VIDEO MULTIPLEXER
JESD-30 代码：	S-PQCC-N24	JESD-609代码：	e3
长度：	4 mm	湿度敏感等级：	1
负电源电压最大值（Vsup）：	-6 V	负电源电压最小值（Vsup）：	-2.25 V
标称负供电电压 (Vsup)：	-5 V	信道数量：	1
功能数量：	3	端子数量：	24
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	VQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	0.75 mm	最大供电电压 (Vsup)：	6 V
最小供电电压 (Vsup)：	2.25 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	BIPOLAR
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	4 mm	Base Number Matches：	1

LT6555IUF 数据手册

LT6555

W U U

APPLICATIO S I FOR ATIO

Power Supplies

The DGND pin should not be pulled above the EN pin since

doing so will turn on an ESD protection diode. If the EN pin

voltageisforcedadiodedropbelowtheDGNDpin,current

should be limited to 10mA or less.

The LT6555 is optimized for ±5V supplies but can be

operated on as little as ±2.25V or a single 4.5V supply and

as much as ±6V or a single 12V supply. Internally, each

supply is independent to improve channel isolation. Do

not leave any supply pins disconnected or the part may

not function correctly!

The enable/disable times of the LT6555 are fast when

driven with a logic input. Turn on (from 50% EN input to

50% output) typically occurs in less than 50ns. Turn off is

slower, but is typically below 500ns.

Enable/Shutdown

The LT6555 has a shutdown mode controlled by the EN

pin and referenced to the DGND pin. If the amplifier will

be enabled at all times, the EN pin can be connected

directly to DGND. If the enable function is desired, either

driving the pin above 2V or allowing the internal 46k pull-

up resistor to pull the EN pin to the top rail will disable the

amplifier. When disabled, the DC output impedance will

rise to approximately 360Ω through the internal feedback

and gain resistors. Supply current into the amplifier in the

disabled state will be:

Channel Select

TheSELpinusesthesameinternalthresholdastheENpin

and is also referenced to DGND. When the pin is logic low,

the channel A inputs are passed to the output. When the

pin is logic high, the channel B inputs are passed to the

output. The pin should not be floated but can be tied to

DGND to force the outputs to always be channel A or to V⁺

(when less than 8V) to force the outputs to always be

channel B.

Truth Table

V⁺– V_EN

46k

V⁺– V^–

80k

SEL A/B

OUT

2 × IN A

2 × IN B

OFF

I_S=

It is important that the following constraints on the DGND,

EN and SEL pins are always followed:

V⁺– V_DGND≥ 4.5V

V_EN– V_DGND≤ 5.5V

V_SEL– V_DGND≤ 8V

Input Considerations

The LT6555 uses input clamps referenced to the V_REFpin

to prevent damage to the input stage on the unselected

channel. Three transistors in series limit the input voltage

to within three diode drops (±) from V_REF. V_REFis nomi-

nally set to half of the sum of the supplies by the 40k

resistors. A simplified schematic is shown in Figure 1.

In dual supply cases where V⁺is less than 4.5V, DGND

should be connected to a potential below ground, such as

V^–. Since the EN and SEL pins are referenced to DGND,

they may need to be pulled below ground in those cases.

In single supply applications above 5.5V, an additional

resistor may be needed from the EN pin to DGND if the pin

is ever allowed to float. For example, on a 12V single

supply, a 33k resistor would protect the pin from floating

too high while still allowing the internal pull-up resistor to

disable the part.

To improve clamping, the pin’s DC impedance should be

minimizedbyconnectingtheV_REFpindirectlytogroundin

the symmetric dual supply case with a common mode

voltage of 0V. While loaded output swing limits the useful

input voltage range in that case, if the common mode

voltage is not centered at ground or the input voltage

exceeds plus or minus three diodes from ground, an

external resistor to either supply can be added to shift the

On dual ±2.25V supplies, connecting the DGND pin to V^–

is the only way of ensuring that V⁺– V_DGND≥ 4.5V.

6555f

1...5 6 789 10 11...16

中文翻译

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