Datasheet > LT1713

LT1713

更新时间： 2024-10-02 22:51:47

品牌	Logo	应用领域
凌特 - Linear		比较器
页数	文件大小	规格书
16页	243K
描述
4ns, 150MHz Dual Comparator with Independent Input/Output Supplies

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数据手册

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LT1713 数据手册

LT1715

4ns, 150MHz

Dual Comparator with

Independent Input/Output Supplies

FEATURES

DESCRIPTIO

The LT^®1715 is an UltraFast^TMdual comparator optimized

for low voltage operation. Separate supplies allow inde-

■

UltraFast: 4ns at 20mV Overdrive

■

150MHz Toggle Frequency

■

Separate Input and Output Power Supplies

Low Power: 4.6mA per Comparator at 3V

Pinout Optimized for High Speed Use

Output Optimized for 3V and 5V Supplies

TTL/CMOS Compatible Rail-to-Rail Output

Input Voltage Range Extends 100mV

Below Negative Rail

pendent analog input ranges and output logic levels with

no loss of performance. The input voltage range extends

from100mVbelowV_EEto1.2VbelowV_CC. Internalhyster-

esis makes the LT1715 easy to use even with slow moving

input signals. The rail-to-rail outputs directly interface to

TTL and CMOS. The symmetric output drive results in

similar rise and fall times that can be harnessed for analog

applications or for easy translation to other single supply

logic levels.

■

Internal Hysteresis with Specified Limits

The LT1715 is available in the 10-pin MSOP package. The

pinout of the LT1715 minimizes parasitic effects by plac-

ing the most sensitive inputs away from the outputs,

shielded by the power rails.

APPLICATIO S

■

High Speed Differential Line Receivers

■

Level Translators

■

Window Comparators

Crystal Oscillator Circuits

Threshold Detectors/Discriminators

High Speed Sampling Circuits

Delay Lines

For a dual/quad single supply comparator with similar

propagation delay, see the LT1720/LT1721. For a single

comparatorwithsimilarpropagationdelay,seetheLT1719.

■

, LTC and LT are registered trademarks of Linear Technology Corporation.

UltraFast is a trademark of Linear Technology Corporation.

■

TYPICAL APPLICATIO

100MHz Dual Differential Line Receiver

Line Receiver Response to 100MHz Clock,

50MHz Data Both with 25mV_P-PInputs

–

CLOCK OUT

1V/DIV

OUT A

OUT B

IN A

IN B

DATA OUT

1V/DIV

–

FET PROBES

5ns/DIV

1715 TA02

1715 TA01

–5V

12 3 4 5 6 7...16

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