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LSU404

更新时间: 2024-01-19 05:31:10
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MICROSS /
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描述
N-CHANNEL JFET

LSU404 技术参数

生命周期:Contact ManufacturerReach Compliance Code:unknown
风险等级:5.67Is Samacsys:N
Base Number Matches:1

LSU404 数据手册

  
LSU404  
LOW NOISE, LOW DRIFT  
MONOLITHIC DUAL  
N-CHANNEL JFET  
Linear Systems replaces discontinued Siliconix U404 with LSU404  
The U404/ LSU404 is a Low Noise, Low Drift, Monolithic Dual N-Channel JFET  
FEATURES  
LOW DRIFT  
LOW NOISE  
LOW PINCHOFF  
The LSU404 is a high-performance monolithic dual  
| V GS12 / T| = 10µV/°C TYP.  
en = 6nV/Hz @ 10Hz TYP.  
Vp = 2.5V TYP.  
JFET featuring extremely low noise, tight offset voltage  
and low drift over temperature specifications, and is  
targeted for use in a wide range of precision  
instrumentation applications. The LSU404 features a 5-  
mV offset and 10-µV/°C drift. The LSU404 is a direct  
replacement for discontinued Siliconix U404.  
ABSOLUTE MAXIMUM RATINGS  
@ 25°C (unless otherwise noted)  
Maximum Temperatures  
Storage Temperature  
Operating Junction Temperature  
The hermetically sealed TO-71 & TO-78 packages are  
well suited for military applications.  
65°C to +150°C  
+150°C  
Maximum Voltage and Current for Each Transistor – Note 1  
(See Packaging Information).  
VGSS  
VDSO  
IG(f)  
Gate Voltage to Drain or Source  
Drain to Source Voltage  
Gate Forward Current  
50V  
50V  
10mA  
U404 / LSU404 Applications:  
Maximum Power Dissipation  
Device Dissipation @ Free Air – Total  
300mW  
ƒ
ƒ
Wideband Differential Amps  
High-Speed,Temp-Compensated Single-  
Ended Input Amps  
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED  
ƒ
ƒ
High-Speed Comparators  
Impedance Converters and vibrations  
detectors.  
SYMBOL  
| V GS12 / T| max.  
CHARACTERISTICS VALUE UNITS CONDITIONS  
DRIFT VS.  
25  
µV/°C  
VDG=10V, ID=200µA  
TA=55°C to +125°C  
VDG=10V, ID=200µA  
TEMPERATURE  
| V GS12 | max.  
OFFSET VOLTAGE  
15  
mV  
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)  
SYMBOL  
BVGSS  
BVGGO  
CHARACTERISTICS  
Breakdown Voltage  
GateToGate Breakdown  
TRANSCONDUCTANCE  
Full Conduction  
MIN.  
50  
±50  
TYP.  
60  
‐‐  
MAX.  
‐‐  
‐‐  
UNITS  
V
V
CONDITIONS  
VDS = 0  
I G= 1nA  
ID=1nA  
ID= 0  
IS= 0  
YfSS  
YfS  
2000  
1000  
‐‐  
‐‐  
7000  
2000  
µmho  
µmho  
VDG= 10V  
VDG= 15V  
VGS= 0V f = 1kHz  
ID= 200µA f = 1kHz  
Typical Operation  
Click To Buy  
|YFS12 / Y FS|  
Mismatch  
DRAIN CURRENT  
Full Conduction  
‐‐  
0.6  
3
%
IDSS  
|IDSS12 / IDSS  
0.5  
‐‐  
‐‐  
1
10  
5
mA  
%
VDG= 10V  
VGS= 0V  
|
Mismatch at Full Conduction  
GATE VOLTAGE  
VGS(off) or Vp  
VGS(on)  
Pinchoff voltage  
Operating Range  
GATE CURRENT  
0.5  
‐‐  
‐‐  
‐‐  
2.5  
2.3  
V
V
VDS= 15V  
VDS=15V  
ID= 1nA  
ID=200µA  
IGmax.  
IGmax.  
IGSSmax.  
IGSSmax.  
Operating  
‐‐  
‐‐  
‐‐  
5
4  
‐‐  
‐‐  
5
15  
10  
100  
5
pA  
nA  
pA  
pA  
VDG= 15V ID= 200µA  
High Temperature  
At Full Conduction  
High Temperature  
OUTPUT CONDUCTANCE  
Full Conduction  
TA= +125°C  
VDS =0  
VDG= 15V  
TA= +125°C  
YOSS  
YOS  
‐‐  
‐‐  
‐‐  
20  
2
µmho  
µmho  
VDG= 10V  
VDG= 15V  
VGS= 0V  
Operating  
0.2  
ID= 500µA  
COMMON MODE REJECTION  
CMR  
20 log | V GS12/ V DS  
|
95  
‐‐  
‐‐  
dB  
VDS = 10 to 20V  
ID=30µA  
NOISE  
Figure  
Voltage  
CAPACITANCE  
Input  
VDS= 15V VGS= 0V  
RG= 10M  
NF  
en  
‐‐  
‐‐  
‐‐  
20  
0.5  
‐‐  
dB  
nV/Hz  
f= 100Hz NBW= 6Hz  
VDS=15V ID=200µA f=10Hz NBW=1Hz  
VDS= 15V ID= 200µA f= 1MHz  
CISS  
CRSS  
‐‐  
‐‐  
‐‐  
‐‐  
8
1.5  
pF  
pF  
Reverse Transfer  
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired  
TO-71 / TO-78 (Top View)  
Micross Components Europe  
Available Packages:  
U404 / LSU404 in TO-71 & TO-78  
U404 / LSU404 available as bare die  
Please contact Micross for full package and die dimensions  
Tel: +44 1603 788967  
Email: chipcomponents@micross.com  
Web: http://www.micross.com/distribution  
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or  
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.  

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