LPC553x
32-bit Arm Cortex®-M33, 128 KB SRAM; 256 KB flash, FlexSPI
with cache, USB FS, Flexcomm Interface, CAN FD, 32-bit
counter/ timers, SCTimer/PWM, 16-bit 2.0 Msamples/sec ADC,
Comparator, 12-bit DAC, OpAmp, FlexPWM Timer, QEI,
Temperature Sensor, CRC
Rev. 4.0 — 18 April 2023
Product data sheet
1. General description
The LPC553x is an ARM Cortex-M33 based microcontroller for embedded applications.
These devices include up to 256 KB on-chip flash, up to 128 KB of on-chip SRAM,
FlexSPI with cache, USB Full-Speed device with crystal-less operation, USB Full-Speed
Host, CAN FD, five general-purpose timers, one SCTimer/PWM, one RTC/alarm timer,
one 24-bit Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), Code
Watchdog Timer, one OS Timer, one Micro-tick timer, eight flexible serial communication
peripherals (Flexcomm Interfaces - which can be configured as a USART, SPI, high speed
SPI, I2C, or I2S interface), one DMIC, one I3C interface, four 16-bit 2.0 Msamples/sec
(four 12-bit 3.2 Msamples/sec) ADC capable of four simultaneous conversions, four
comparators, two temperature sensors, three 12-bit 1 Msample/sec DAC, 3 OpAmps, two
FlexPWM timers, and two QEIs.
2. Features and benefits
ARM® Cortex-M33 core (r0p4):
Running at a frequency of up to 150 MHz.
Integrated digital signal processing (DSP) instructions.
Floating Point Unit (FPU) and Memory Protection Unit (MPU).
ARM Cortex M33 built-in Nested Vectored Interrupt Controller (NVIC).
Non-maskable Interrupt (NMI) input with a selection of sources.
Serial Wire Debug with eight breakpoints and four watch points. Includes Serial
Wire Output for enhanced debug capabilities and trace (ETM).
System tick timer.
A hardware DSP accelerator for fixed and floating point DSP functions (PowerQuad).
PowerQuad uses a bank of four dedicated 4 KB SRAMs
On-chip memory:
Up to 256 KB on-chip flash program memory, with flash accelerator and 512 byte
page erase and write, coupled with 8 KB Low Power Cache to enhance system
performance.
Up to 128 KB total SRAM consisting of 16 KB SRAM on Code Bus, 112 KB SRAM
on System Bus (112 KB is contiguous).
Parity support on all RAM banks except RAM1 bank. ECC support available only
on RAM1 bank.
OTP eFuse programmable memory.