Datasheet > LPC43S37JBD144

LPC43S37JBD144

更新时间： 2024-03-03 10:09:36

品牌	Logo	应用领域
恩智浦 - NXP		静态存储器
页数	文件大小	规格书
157页	7250K
描述
32-Bit Arm^® Cortex^®-M4/M0 MCU; 1 MB Flash and 136 KB SRAM; Ethernet, 2...

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LPC43S37JBD144 数据手册

LPC43S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M4/M0 microcontroller

 ARM Cortex-M0 coprocessor (version r0p0) capable of off-loading the main ARM

Cortex-M4 application processor.

 Running at frequencies of up to 204 MHz.

 JTAG

 Built-in NVIC.

 On-chip memory

 Up to 1 MB on-chip dual bank flash memory with flash accelerator.

 16 kB on-chip EEPROM data memory.

 136 kB SRAM for code and data use.

 Multiple SRAM blocks with separate bus access. Two SRAM blocks can be

powered down individually.

 64 kB ROM containing boot code and on-chip software drivers.

 64 bit of One-Time Programmable (OTP) memory for general-purpose use.

 Two banks (256 bit total) One-Time Programmable (OTP) memory for AES key

storage. One bank can store an encrypted key for decoding the boot image.

 AES engine for encryption and decryption of the boot image and data with DMA

support and programmable via a ROM-based API.

 Configurable digital peripherals

 Serial GPIO (SGPIO) interface.

 State Configurable Timer (SCT) subsystem on AHB.

 Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and

outputs to event driven peripherals like the timers, SCT, and ADC0/1.

 Serial interfaces

 Quad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB per second.

 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high

throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time

stamping (IEEE 1588-2008 v2).

 One High-speed USB 2.0 Host/Device/OTG interface with DMA support and

on-chip high-speed PHY.

 One High-speed USB 2.0 Host/Device interface with DMA support, on-chip

full-speed PHY and ULPI interface to external high-speed PHY.

 USB interface electrical test software included in ROM USB stack.

 One 550 UART with DMA support and full modem interface.

 Three 550 USARTs with DMA and synchronous mode support and a smart card

interface conforming to ISO7816 specification. One USART with IrDA interface.

 Up to two C_CAN 2.0B controllers with one channel each.

 Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA

support.

 One SPI controller.

 One Fast-mode Plus I²C-bus interface with monitor mode and with open-drain I/O

pins conforming to the full I²C-bus specification. Supports data rates of up to

1 Mbit/s.

 One standard I²C-bus interface with monitor mode and with standard I/O pins.

 Two I²S interfaces, each with DMA support and with one input and one output.

 Digital peripherals

LPC43S5X_S3X

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 13 January 2020

2 of 157

123 4 5 6 7...157

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