Datasheet > LPC18S10FBD144

LPC18S10FBD144

更新时间： 2024-03-03 10:07:57

品牌	Logo	应用领域
恩智浦 - NXP		静态存储器
页数	文件大小	规格书
152页	6904K
描述
32-bit ARM Cortex-M3 flashless MCU with security features; 136 kB SRAM; EMC

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LPC18S10FBD144 数据手册

LPC18S50/S30/S10

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

109

144

LPC18S30/10FBD144

aaa-014018

Fig 5. Pin configuration LQFP144 package

6.2 Pin description

On the LPC18S50/S30/S10, digital pins are grouped into 16 ports, named P0 to P9 and

PA to PF, with up to 20 pins used per port. Each digital pin can support up to eight different

digital functions, including General-Purpose I/O (GPIO), selectable through the System

Configuration Unit (SCU) registers. The pin name is not indicative of the GPIO port

assigned to it.

Not all functions listed in Table 3 are available on all packages. See Table 2 for availability

of USB0, USB1, Ethernet, and LCD functions.

The parts contain two 10-bit ADCs (ADC0 and ADC1). The input channels of ADC0 and

ADC1 on dedicated pins and multiplexed pins are combined in such a way that all channel

0 inputs (named ADC0_0 and ADC1_0) are tied together and connected to both, channel

0 on ADC0 and channel 0 on ADC1, channel 1 inputs (named ADC0_1 and ADC1_1) are

tied together and connected to channel 1 on ADC0 and ADC1, and so forth. There are

eight ADC channels total for the two ADCs.

LPC18S50_S30_S10

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 10 January 2020

7 of 152

1...4 5 678 9 10...152

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